^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2019, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slimbus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/soundwire/sdw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/soundwire/sdw_registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <sound/pcm_params.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <sound/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "bus.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SWRM_COMP_HW_VERSION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SWRM_COMP_CFG_ADDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SWRM_COMP_CFG_ENABLE_MSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SWRM_COMP_PARAMS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SWRM_COMP_PARAMS_DOUT_PORTS_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SWRM_COMP_PARAMS_DIN_PORTS_MASK GENMASK(9, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SWRM_INTERRUPT_STATUS 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SWRM_INTERRUPT_STATUS_RMSK GENMASK(16, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SWRM_INTERRUPT_STATUS_CMD_ERROR BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SWRM_INTERRUPT_MASK_ADDR 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SWRM_INTERRUPT_CLEAR 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SWRM_INTERRUPT_CPU_EN 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SWRM_CMD_FIFO_WR_CMD 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SWRM_CMD_FIFO_RD_CMD 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SWRM_CMD_FIFO_CMD 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SWRM_CMD_FIFO_STATUS 0x30C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SWRM_CMD_FIFO_CFG_ADDR 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SWRM_RD_WR_CMD_RETRIES 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SWRM_CMD_FIFO_RD_FIFO_ADDR 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SWRM_ENUMERATOR_CFG_ADDR 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (0x101C + 0x40 * (m))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK GENMASK(7, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SWRM_MCP_CFG_ADDR 0x1048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK GENMASK(21, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SWRM_DEF_CMD_NO_PINGS 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SWRM_MCP_STATUS 0x104C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SWRM_MCP_STATUS_BANK_NUM_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SWRM_MCP_SLV_STATUS 0x1090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SWRM_AHB_BRIDGE_WR_DATA_0 0xc85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SWRM_AHB_BRIDGE_WR_ADDR_0 0xc89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SWRM_AHB_BRIDGE_RD_ADDR_0 0xc8d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SWRM_AHB_BRIDGE_RD_DATA_0 0xc91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SWRM_REG_VAL_PACK(data, dev, id, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SWRM_SPECIAL_CMD_ID 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MAX_FREQ_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TIMEOUT_MS (2 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QCOM_SWRM_MAX_RD_LEN 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define QCOM_SDW_MAX_PORTS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DEFAULT_CLK_FREQ 9600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SWRM_MAX_DAIS 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct qcom_swrm_port_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 si;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 off1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 off2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 bp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct qcom_swrm_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct sdw_bus bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct completion *comp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct work_struct slave_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* read/write lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spinlock_t comp_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Port alloc/free lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct mutex port_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 wr_cmd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 rd_cmd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int num_din_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int num_dout_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int cols_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int rows_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long dout_port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long din_port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct qcom_swrm_port_config pconfig[QCOM_SDW_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct sdw_stream_runtime *sruntime[SWRM_MAX_DAIS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum sdw_slave_status status[SDW_MAX_DEVICES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct qcom_swrm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 default_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 default_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct qcom_swrm_data swrm_v1_3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .default_rows = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .default_cols = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct qcom_swrm_data swrm_v1_5_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .default_rows = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .default_cols = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct regmap *wcd_regmap = ctrl->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* pg register + offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_RD_ADDR_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (u8 *)®, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return SDW_CMD_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = regmap_bulk_read(wcd_regmap, SWRM_AHB_BRIDGE_RD_DATA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return SDW_CMD_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return SDW_CMD_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct regmap *wcd_regmap = ctrl->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* pg register + offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_DATA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) (u8 *)&val, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return SDW_CMD_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* write address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = regmap_bulk_write(wcd_regmap, SWRM_AHB_BRIDGE_WR_ADDR_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (u8 *)®, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return SDW_CMD_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return SDW_CMD_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *val = readl(ctrl->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return SDW_CMD_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) writel(val, ctrl->mmio + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return SDW_CMD_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 dev_addr, u16 reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DECLARE_COMPLETION_ONSTACK(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) spin_lock_irqsave(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ctrl->comp = ∁
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) spin_unlock_irqrestore(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val = SWRM_REG_VAL_PACK(cmd_data, dev_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SWRM_SPECIAL_CMD_ID, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ret = wait_for_completion_timeout(ctrl->comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) msecs_to_jiffies(TIMEOUT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = SDW_CMD_IGNORED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = SDW_CMD_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) spin_lock_irqsave(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ctrl->comp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) spin_unlock_irqrestore(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 dev_addr, u16 reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 len, u8 *rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DECLARE_COMPLETION_ONSTACK(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) spin_lock_irqsave(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ctrl->comp = ∁
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) spin_unlock_irqrestore(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) val = SWRM_REG_VAL_PACK(len, dev_addr, SWRM_SPECIAL_CMD_ID, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = wait_for_completion_timeout(ctrl->comp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) msecs_to_jiffies(TIMEOUT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = SDW_CMD_IGNORED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = SDW_CMD_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ctrl->reg_read(ctrl, SWRM_CMD_FIFO_RD_FIFO_ADDR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rval[i] = val & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) spin_lock_irqsave(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ctrl->comp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) spin_unlock_irqrestore(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (i = 0; i < SDW_MAX_DEVICES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) s = (val >> (i * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) s &= SWRM_MCP_SLV_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ctrl->status[i] = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static irqreturn_t qcom_swrm_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct qcom_swrm_ctrl *ctrl = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 sts, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ctrl->reg_read(ctrl, SWRM_INTERRUPT_STATUS, &sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (sts & SWRM_INTERRUPT_STATUS_CMD_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ctrl->reg_read(ctrl, SWRM_CMD_FIFO_STATUS, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_err_ratelimited(ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "CMD error, fifo status 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if ((sts & SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) sts & SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) schedule_work(&ctrl->slave_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * clear the interrupt before complete() is called, as complete can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * schedule new read/writes which require interrupts, clearing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * interrupt would avoid missing interrupts in such cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (sts & SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) spin_lock_irqsave(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ctrl->comp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) complete(ctrl->comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) spin_unlock_irqrestore(&ctrl->comp_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Clear Rows and Cols */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Disable Auto enumeration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Mask soundwire interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SWRM_INTERRUPT_STATUS_RMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Configure No pings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32p_replace_bits(&val, SWRM_DEF_CMD_NO_PINGS, SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Configure number of retries of a read/write cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, SWRM_RD_WR_CMD_RETRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Set IRQ to PULSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SWRM_COMP_CFG_ENABLE_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* enable CPU IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ctrl->mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SWRM_INTERRUPT_STATUS_RMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static enum sdw_command_response qcom_swrm_xfer_msg(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct sdw_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int ret, i, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (msg->flags == SDW_MSG_FLAG_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) for (i = 0; i < msg->len;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) len = msg->len - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) len = QCOM_SWRM_MAX_RD_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) msg->addr + i, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &msg->buf[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) i = i + len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else if (msg->flags == SDW_MSG_FLAG_WRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) for (i = 0; i < msg->len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) msg->dev_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) msg->addr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return SDW_CMD_IGNORED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return SDW_CMD_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int qcom_swrm_pre_bank_switch(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ctrl->reg_read(ctrl, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ctrl->reg_write(ctrl, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int qcom_swrm_port_params(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct sdw_port_params *p_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* TBD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int qcom_swrm_transport_params(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct sdw_transport_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) enum sdw_reg_bank bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) value = params->offset1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) value |= params->offset2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) value |= params->sample_interval - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = ctrl->reg_write(ctrl, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!ret && params->blk_pkg_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = ctrl->reg_write(ctrl, reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int qcom_swrm_port_enable(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct sdw_enable_ch *enable_ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ctrl->reg_read(ctrl, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (enable_ch->enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) val &= ~(0xff << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ctrl->reg_write(ctrl, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct sdw_master_port_ops qcom_swrm_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .dpn_set_port_params = qcom_swrm_port_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .dpn_set_port_transport_params = qcom_swrm_transport_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .dpn_port_enable_ch = qcom_swrm_port_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct sdw_master_ops qcom_swrm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .xfer_msg = qcom_swrm_xfer_msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .pre_bank_switch = qcom_swrm_pre_bank_switch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int qcom_swrm_compute_params(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct sdw_master_runtime *m_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct sdw_slave_runtime *s_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct sdw_port_runtime *p_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct qcom_swrm_port_config *pcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pcfg = &ctrl->pconfig[p_rt->num - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) p_rt->transport_params.port_num = p_rt->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) p_rt->transport_params.sample_interval = pcfg->si + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) p_rt->transport_params.offset1 = pcfg->off1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) p_rt->transport_params.offset2 = pcfg->off2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pcfg = &ctrl->pconfig[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) p_rt->transport_params.port_num = p_rt->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) p_rt->transport_params.sample_interval =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pcfg->si + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) p_rt->transport_params.offset1 = pcfg->off1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) p_rt->transport_params.offset2 = pcfg->off2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static u32 qcom_swrm_freq_tbl[MAX_FREQ_NUM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DEFAULT_CLK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void qcom_swrm_slave_wq(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct qcom_swrm_ctrl *ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) container_of(work, struct qcom_swrm_ctrl, slave_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) qcom_swrm_get_device_status(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) sdw_handle_slave_status(&ctrl->bus, ctrl->status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct sdw_stream_runtime *stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct sdw_master_runtime *m_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct sdw_port_runtime *p_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned long *port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mutex_lock(&ctrl->port_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) list_for_each_entry(m_rt, &stream->master_list, stream_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (m_rt->direction == SDW_DATA_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) port_mask = &ctrl->dout_port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) port_mask = &ctrl->din_port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) list_for_each_entry(p_rt, &m_rt->port_list, port_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clear_bit(p_rt->num - 1, port_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) mutex_unlock(&ctrl->port_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct sdw_stream_runtime *stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct sdw_port_config pconfig[QCOM_SDW_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct sdw_stream_config sconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct sdw_master_runtime *m_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct sdw_slave_runtime *s_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct sdw_port_runtime *p_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned long *port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int i, maxport, pn, nports = 0, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mutex_lock(&ctrl->port_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) list_for_each_entry(m_rt, &stream->master_list, stream_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (m_rt->direction == SDW_DATA_DIR_RX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) maxport = ctrl->num_dout_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) port_mask = &ctrl->dout_port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) maxport = ctrl->num_din_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) port_mask = &ctrl->din_port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Port numbers start from 1 - 14*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pn = find_first_zero_bit(port_mask, maxport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (pn > (maxport - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dev_err(ctrl->dev, "All ports busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) set_bit(pn, port_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pconfig[nports].num = pn + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pconfig[nports].ch_mask = p_rt->ch_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) nports++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (direction == SNDRV_PCM_STREAM_CAPTURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sconfig.direction = SDW_DATA_DIR_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) sconfig.direction = SDW_DATA_DIR_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* hw parameters wil be ignored as we only support PDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) sconfig.ch_count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) sconfig.frame_rate = params_rate(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sconfig.type = stream->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) sconfig.bps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) nports, stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (i = 0; i < nports; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) clear_bit(pconfig[i].num - 1, port_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mutex_unlock(&ctrl->port_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int qcom_swrm_hw_params(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct snd_pcm_hw_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) qcom_swrm_stream_free_ports(ctrl, sruntime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int qcom_swrm_hw_free(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) qcom_swrm_stream_free_ports(ctrl, sruntime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) sdw_stream_remove_master(&ctrl->bus, sruntime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int qcom_swrm_set_sdw_stream(struct snd_soc_dai *dai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) void *stream, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ctrl->sruntime[dai->id] = stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static void *qcom_swrm_get_sdw_stream(struct snd_soc_dai *dai, int direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ctrl->sruntime[dai->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int qcom_swrm_startup(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct snd_soc_pcm_runtime *rtd = substream->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct sdw_stream_runtime *sruntime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct snd_soc_dai *codec_dai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) sruntime = sdw_alloc_stream(dai->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!sruntime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ctrl->sruntime[dai->id] = sruntime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) for_each_rtd_codec_dais(rtd, i, codec_dai) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = snd_soc_dai_set_sdw_stream(codec_dai, sruntime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) substream->stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (ret < 0 && ret != -ENOTSUPP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dev_err(dai->dev, "Failed to set sdw stream on %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) codec_dai->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) sdw_release_stream(sruntime);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static void qcom_swrm_shutdown(struct snd_pcm_substream *substream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct snd_soc_dai *dai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) sdw_release_stream(ctrl->sruntime[dai->id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ctrl->sruntime[dai->id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct snd_soc_dai_ops qcom_swrm_pdm_dai_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .hw_params = qcom_swrm_hw_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .hw_free = qcom_swrm_hw_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .startup = qcom_swrm_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .shutdown = qcom_swrm_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .set_sdw_stream = qcom_swrm_set_sdw_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .get_sdw_stream = qcom_swrm_get_sdw_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static const struct snd_soc_component_driver qcom_swrm_dai_component = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .name = "soundwire",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct snd_soc_dai_driver *dais;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct snd_soc_pcm_stream *stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct device *dev = ctrl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* PDM dais are only tested for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dais = devm_kcalloc(dev, num_dais, sizeof(*dais), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!dais)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) for (i = 0; i < num_dais; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dais[i].name = devm_kasprintf(dev, GFP_KERNEL, "SDW Pin%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!dais[i].name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (i < ctrl->num_dout_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) stream = &dais[i].playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) stream = &dais[i].capture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) stream->channels_min = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) stream->channels_max = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) stream->rates = SNDRV_PCM_RATE_48000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) stream->formats = SNDRV_PCM_FMTBIT_S16_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dais[i].ops = &qcom_swrm_pdm_dai_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dais[i].id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return devm_snd_soc_register_component(ctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) &qcom_swrm_dai_component,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dais, num_dais);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct device_node *np = ctrl->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u8 off1[QCOM_SDW_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u8 off2[QCOM_SDW_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 si[QCOM_SDW_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u8 bp_mode[QCOM_SDW_MAX_PORTS] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int i, ret, nports, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = of_property_read_u32(np, "qcom,din-ports", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (val > ctrl->num_din_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ctrl->num_din_ports = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = of_property_read_u32(np, "qcom,dout-ports", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (val > ctrl->num_dout_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ctrl->num_dout_ports = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) nports = ctrl->num_dout_ports + ctrl->num_din_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = of_property_read_u8_array(np, "qcom,ports-offset1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) off1, nports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = of_property_read_u8_array(np, "qcom,ports-offset2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) off2, nports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) si, nports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) bp_mode, nports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) for (i = 0; i < nports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ctrl->pconfig[i].si = si[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ctrl->pconfig[i].off1 = off1[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ctrl->pconfig[i].off2 = off2[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ctrl->pconfig[i].bp_mode = bp_mode[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int qcom_swrm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct sdw_master_prop *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct sdw_bus_params *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct qcom_swrm_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) const struct qcom_swrm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ctrl->rows_index = sdw_find_row_index(data->default_rows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ctrl->cols_index = sdw_find_col_index(data->default_cols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #if IS_REACHABLE(CONFIG_SLIMBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (dev->parent->bus == &slimbus_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ctrl->reg_read = qcom_swrm_ahb_reg_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ctrl->reg_write = qcom_swrm_ahb_reg_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ctrl->regmap = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!ctrl->regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ctrl->reg_read = qcom_swrm_cpu_reg_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ctrl->reg_write = qcom_swrm_cpu_reg_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (IS_ERR(ctrl->mmio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return PTR_ERR(ctrl->mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ctrl->irq = of_irq_get(dev->of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (ctrl->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = ctrl->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ctrl->hclk = devm_clk_get(dev, "iface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (IS_ERR(ctrl->hclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ret = PTR_ERR(ctrl->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) clk_prepare_enable(ctrl->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ctrl->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_set_drvdata(&pdev->dev, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) spin_lock_init(&ctrl->comp_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) mutex_init(&ctrl->port_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) INIT_WORK(&ctrl->slave_work, qcom_swrm_slave_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ctrl->bus.ops = &qcom_swrm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ctrl->bus.port_ops = &qcom_swrm_port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ctrl->bus.compute_params = &qcom_swrm_compute_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = qcom_swrm_get_port_config(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) params = &ctrl->bus.params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) params->max_dr_freq = DEFAULT_CLK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) params->curr_dr_freq = DEFAULT_CLK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) params->col = data->default_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) params->row = data->default_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) params->next_bank = !params->curr_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) prop = &ctrl->bus.prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) prop->max_clk_freq = DEFAULT_CLK_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) prop->num_clk_gears = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) prop->num_clk_freq = MAX_FREQ_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) prop->clk_freq = &qcom_swrm_freq_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) prop->default_col = data->default_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) prop->default_row = data->default_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) qcom_swrm_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) IRQF_TRIGGER_RISING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "soundwire", ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_err(dev, "Failed to request soundwire irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev_err(dev, "Failed to register Soundwire controller (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) qcom_swrm_init(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret = qcom_swrm_register_dais(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) goto err_master_add;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_info(dev, "Qualcomm Soundwire controller v%x.%x.%x Registered\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ctrl->version & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) err_master_add:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) sdw_bus_master_delete(&ctrl->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) clk_disable_unprepare(ctrl->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) err_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int qcom_swrm_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) sdw_bus_master_delete(&ctrl->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) clk_disable_unprepare(ctrl->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static const struct of_device_id qcom_swrm_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {/* sentinel */},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MODULE_DEVICE_TABLE(of, qcom_swrm_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static struct platform_driver qcom_swrm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .probe = &qcom_swrm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .remove = &qcom_swrm_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .name = "qcom-soundwire",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .of_match_table = qcom_swrm_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) module_platform_driver(qcom_swrm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) MODULE_DESCRIPTION("Qualcomm soundwire driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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