Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // Copyright(c) 2015-2020 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Bandwidth management algorithm based on 2^n gears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/soundwire/sdw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "bus.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SDW_STRM_RATE_GROUPING		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct sdw_group_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	int full_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	int payload_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	int hwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct sdw_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	unsigned int max_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	unsigned int *rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct sdw_transport_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	int hstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	int hstop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	int block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	int sub_block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static void sdw_compute_slave_ports(struct sdw_master_runtime *m_rt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 				    struct sdw_transport_data *t_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct sdw_slave_runtime *s_rt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct sdw_port_runtime *p_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int port_bo, sample_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned int rate, bps, ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int slave_total_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct sdw_bus_params *b_params = &m_rt->bus->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	port_bo = t_data->block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		rate = m_rt->stream->params.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		bps = m_rt->stream->params.bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		sample_int = (m_rt->bus->params.curr_dr_freq / rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		slave_total_ch = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 			ch = sdw_ch_mask_to_ch(p_rt->ch_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			sdw_fill_xport_params(&p_rt->transport_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 					      p_rt->num, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 					      SDW_BLK_GRP_CNT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 					      sample_int, port_bo, port_bo >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 					      t_data->hstart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 					      t_data->hstop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 					      (SDW_BLK_GRP_CNT_1 * ch), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 			sdw_fill_port_params(&p_rt->port_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 					     p_rt->num, bps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 					     SDW_PORT_FLOW_MODE_ISOCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 					     b_params->s_data_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			port_bo += bps * ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			slave_total_ch += ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		if (m_rt->direction == SDW_DATA_DIR_TX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		    m_rt->ch_count == slave_total_ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			 * Slave devices were configured to access all channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			 * of the stream, which indicates that they operate in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			 * 'mirror mode'. Make sure we reset the port offset for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			 * the next device in the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			port_bo = t_data->block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void sdw_compute_master_ports(struct sdw_master_runtime *m_rt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				     struct sdw_group_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				     int port_bo, int hstop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct sdw_transport_data t_data = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct sdw_port_runtime *p_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct sdw_bus *bus = m_rt->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct sdw_bus_params *b_params = &bus->params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int sample_int, hstart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned int rate, bps, ch, no_ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	rate = m_rt->stream->params.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	bps = m_rt->stream->params.bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	ch = m_rt->ch_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	sample_int = (bus->params.curr_dr_freq / rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	if (rate != params->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	t_data.hstop = hstop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	hstart = hstop - params->hwidth + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	t_data.hstart = hstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		no_ch = sdw_ch_mask_to_ch(p_rt->ch_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		sdw_fill_xport_params(&p_rt->transport_params, p_rt->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				      false, SDW_BLK_GRP_CNT_1, sample_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				      port_bo, port_bo >> 8, hstart, hstop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				      (SDW_BLK_GRP_CNT_1 * no_ch), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		sdw_fill_port_params(&p_rt->port_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				     p_rt->num, bps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				     SDW_PORT_FLOW_MODE_ISOCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				     b_params->m_data_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		/* Check for first entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		if (!(p_rt == list_first_entry(&m_rt->port_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 					       struct sdw_port_runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 					       port_node))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			port_bo += bps * ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		t_data.hstart = hstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		t_data.hstop = hstop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		t_data.block_offset = port_bo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		t_data.sub_block_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		port_bo += bps * ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	sdw_compute_slave_ports(m_rt, &t_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void _sdw_compute_port_params(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				     struct sdw_group_params *params, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct sdw_master_runtime *m_rt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int hstop = bus->params.col - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int block_offset, port_bo, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* Run loop for all groups to compute transport parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		port_bo = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		block_offset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			sdw_compute_master_ports(m_rt, &params[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 						 port_bo, hstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			block_offset += m_rt->ch_count *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 					m_rt->stream->params.bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			port_bo = block_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		hstop = hstop - params[i].hwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int sdw_compute_group_params(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				    struct sdw_group_params *params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 				    int *rates, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	struct sdw_master_runtime *m_rt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	int sel_col = bus->params.col;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	unsigned int rate, bps, ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int i, column_needed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* Calculate bandwidth per group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		params[i].rate = rates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		params[i].full_bw = bus->params.curr_dr_freq / params[i].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		rate = m_rt->stream->params.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		bps = m_rt->stream->params.bps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		ch = m_rt->ch_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			if (rate == params[i].rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				params[i].payload_bw += bps * ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		params[i].hwidth = (sel_col *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			params[i].payload_bw + params[i].full_bw - 1) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			params[i].full_bw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		column_needed += params[i].hwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (column_needed > sel_col - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int sdw_add_element_group_count(struct sdw_group *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				       unsigned int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int num = group->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	for (i = 0; i <= num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		if (rate == group->rates[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (i != num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		if (group->count >= group->max_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			unsigned int *rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			group->max_size += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			rates = krealloc(group->rates,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 					 (sizeof(int) * group->max_size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					 GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			if (!rates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			group->rates = rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		group->rates[group->count++] = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int sdw_get_group_count(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 			       struct sdw_group *group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct sdw_master_runtime *m_rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	unsigned int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	group->count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	group->max_size = SDW_STRM_RATE_GROUPING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	group->rates = kcalloc(group->max_size, sizeof(int), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (!group->rates)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		rate = m_rt->stream->params.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		if (m_rt == list_first_entry(&bus->m_rt_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 					     struct sdw_master_runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 					     bus_node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			group->rates[group->count++] = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			ret = sdw_add_element_group_count(group, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				kfree(group->rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * sdw_compute_port_params: Compute transport and port parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * @bus: SDW Bus instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int sdw_compute_port_params(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct sdw_group_params *params = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	struct sdw_group group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	ret = sdw_get_group_count(bus, &group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (group.count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	params = kcalloc(group.count, sizeof(*params), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (!params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* Compute transport parameters for grouped streams */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	ret = sdw_compute_group_params(bus, params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				       &group.rates[0], group.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		goto free_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	_sdw_compute_port_params(bus, params, group.count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) free_params:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	kfree(params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	kfree(group.rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int sdw_select_row_col(struct sdw_bus *bus, int clk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct sdw_master_prop *prop = &bus->prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int frame_int, frame_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int r, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	for (c = 0; c < SDW_FRAME_COLS; c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		for (r = 0; r < SDW_FRAME_ROWS; r++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			if (sdw_rows[r] != prop->default_row ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			    sdw_cols[c] != prop->default_col)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			frame_int = sdw_rows[r] * sdw_cols[c];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			frame_freq = clk_freq / frame_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			if ((clk_freq - (frame_freq * SDW_FRAME_CTRL_BITS)) <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			    bus->params.bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			bus->params.row = sdw_rows[r];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			bus->params.col = sdw_cols[c];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)  * sdw_compute_bus_params: Compute bus parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)  * @bus: SDW Bus instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int sdw_compute_bus_params(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	unsigned int max_dr_freq, curr_dr_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	struct sdw_master_prop *mstr_prop = &bus->prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	int i, clk_values, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	bool is_gear = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	u32 *clk_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (mstr_prop->num_clk_gears) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		clk_values = mstr_prop->num_clk_gears;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		clk_buf = mstr_prop->clk_gears;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		is_gear = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	} else if (mstr_prop->num_clk_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		clk_values = mstr_prop->num_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		clk_buf = mstr_prop->clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		clk_values = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		clk_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	max_dr_freq = mstr_prop->max_clk_freq * SDW_DOUBLE_RATE_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	for (i = 0; i < clk_values; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		if (!clk_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			curr_dr_freq = max_dr_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			curr_dr_freq = (is_gear) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 				(max_dr_freq >>  clk_buf[i]) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 				clk_buf[i] * SDW_DOUBLE_RATE_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		if (curr_dr_freq <= bus->params.bandwidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		 * TODO: Check all the Slave(s) port(s) audio modes and find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		 * whether given clock rate is supported with glitchless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		 * transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (i == clk_values)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	ret = sdw_select_row_col(bus, curr_dr_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	bus->params.curr_dr_freq = curr_dr_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)  * sdw_compute_params: Compute bus, transport and port parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)  * @bus: SDW Bus instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int sdw_compute_params(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	/* Computes clock frequency, frame shape and frame frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	ret = sdw_compute_bus_params(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		dev_err(bus->dev, "Compute bus params failed: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	/* Compute transport and port params */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	ret = sdw_compute_port_params(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		dev_err(bus->dev, "Compute transport params failed: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) EXPORT_SYMBOL(sdw_compute_params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MODULE_DESCRIPTION("SoundWire Generic Bandwidth Allocation");