^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright(c) 2015-17 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/soundwire/sdw_registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/soundwire/sdw.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "bus.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "sysfs_local.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static DEFINE_IDA(sdw_ida);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static int sdw_get_id(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int rc = ida_alloc(&sdw_ida, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) bus->id = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * sdw_bus_master_add() - add a bus Master instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @bus: bus instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @parent: parent device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @fwnode: firmware node handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Initializes the bus instance, read properties and create child
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct fwnode_handle *fwnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct sdw_master_prop *prop = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pr_err("SoundWire parent device is not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ret = sdw_get_id(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dev_err(parent, "Failed to get bus id\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ret = sdw_master_device_add(bus, parent, fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dev_err(parent, "Failed to add master device at link %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bus->link_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!bus->ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_err(bus->dev, "SoundWire Bus ops are not set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!bus->compute_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "Bandwidth allocation not configured, compute_params no set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mutex_init(&bus->msg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mutex_init(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) INIT_LIST_HEAD(&bus->slaves);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) INIT_LIST_HEAD(&bus->m_rt_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Initialize multi_link flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * TODO: populate this flag by reading property from FW node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bus->multi_link = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (bus->ops->read_prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = bus->ops->read_prop(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "Bus read properties failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) sdw_bus_debugfs_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Device numbers in SoundWire are 0 through 15. Enumeration device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * number (0), Broadcast device number (15), Group numbers (12 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 13) and Master device number (14) are not used for assignment so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * mask these and other higher bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Set higher order bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *bus->assigned = ~GENMASK(SDW_BROADCAST_DEV_NUM, SDW_ENUM_DEV_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Set enumuration device number and broadcast device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) set_bit(SDW_ENUM_DEV_NUM, bus->assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) set_bit(SDW_BROADCAST_DEV_NUM, bus->assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Set group device numbers and master device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) set_bit(SDW_GROUP12_DEV_NUM, bus->assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) set_bit(SDW_GROUP13_DEV_NUM, bus->assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) set_bit(SDW_MASTER_DEV_NUM, bus->assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * SDW is an enumerable bus, but devices can be powered off. So,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * they won't be able to report as present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Create Slave devices based on Slaves described in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * the respective firmware (ACPI/DT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (IS_ENABLED(CONFIG_ACPI) && ACPI_HANDLE(bus->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) ret = sdw_acpi_find_slaves(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else if (IS_ENABLED(CONFIG_OF) && bus->dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = sdw_of_find_slaves(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = -ENOTSUPP; /* No ACPI/DT so error out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_err(bus->dev, "Finding slaves failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Initialize clock values based on Master properties. The max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * frequency is read from max_clk_freq property. Current assumption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * is that the bus will start at highest clock frequency when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * powered on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Default active bank will be 0 as out of reset the Slaves have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * to start with bank 0 (Table 40 of Spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) prop = &bus->prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bus->params.max_dr_freq = prop->max_clk_freq * SDW_DOUBLE_RATE_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bus->params.curr_dr_freq = bus->params.max_dr_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bus->params.curr_bank = SDW_BANK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bus->params.next_bank = SDW_BANK1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EXPORT_SYMBOL(sdw_bus_master_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int sdw_delete_slave(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct sdw_slave *slave = dev_to_sdw_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct sdw_bus *bus = slave->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) sdw_slave_debugfs_exit(slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mutex_lock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (slave->dev_num) /* clear dev_num if assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clear_bit(slave->dev_num, bus->assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) list_del_init(&slave->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) mutex_unlock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) device_unregister(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * sdw_bus_master_delete() - delete the bus master instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @bus: bus to be deleted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Remove the instance, delete the child devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void sdw_bus_master_delete(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) device_for_each_child(bus->dev, NULL, sdw_delete_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sdw_master_device_del(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) sdw_bus_debugfs_exit(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ida_free(&sdw_ida, bus->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) EXPORT_SYMBOL(sdw_bus_master_delete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * SDW IO Calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline int find_response_code(enum sdw_command_response resp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) switch (resp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case SDW_CMD_OK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case SDW_CMD_IGNORED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case SDW_CMD_TIMEOUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline int do_transfer(struct sdw_bus *bus, struct sdw_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int retry = bus->prop.err_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum sdw_command_response resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) for (i = 0; i <= retry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) resp = bus->ops->xfer_msg(bus, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = find_response_code(resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* if cmd is ok or ignored return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ret == 0 || ret == -ENODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static inline int do_transfer_defer(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct sdw_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct sdw_defer *defer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int retry = bus->prop.err_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) enum sdw_command_response resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) defer->msg = msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) defer->length = msg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) init_completion(&defer->complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (i = 0; i <= retry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) resp = bus->ops->xfer_msg_defer(bus, msg, defer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = find_response_code(resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* if cmd is ok or ignored return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ret == 0 || ret == -ENODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int sdw_reset_page(struct sdw_bus *bus, u16 dev_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int retry = bus->prop.err_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) enum sdw_command_response resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int ret = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for (i = 0; i <= retry; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) resp = bus->ops->reset_page_addr(bus, dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = find_response_code(resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* if cmd is ok or ignored return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (ret == 0 || ret == -ENODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int sdw_transfer_unlocked(struct sdw_bus *bus, struct sdw_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = do_transfer(bus, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (ret != 0 && ret != -ENODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) dev_err(bus->dev, "trf on Slave %d failed:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) msg->dev_num, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (msg->page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sdw_reset_page(bus, msg->dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * sdw_transfer() - Synchronous transfer message to a SDW Slave device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @bus: SDW bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @msg: SDW message to be xfered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int sdw_transfer(struct sdw_bus *bus, struct sdw_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mutex_lock(&bus->msg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = sdw_transfer_unlocked(bus, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mutex_unlock(&bus->msg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * sdw_transfer_defer() - Asynchronously transfer message to a SDW Slave device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @bus: SDW bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @msg: SDW message to be xfered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @defer: Defer block for signal completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Caller needs to hold the msg_lock lock while calling this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int sdw_transfer_defer(struct sdw_bus *bus, struct sdw_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct sdw_defer *defer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!bus->ops->xfer_msg_defer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = do_transfer_defer(bus, msg, defer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret != 0 && ret != -ENODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dev_err(bus->dev, "Defer trf on Slave %d failed:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) msg->dev_num, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (msg->page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) sdw_reset_page(bus, msg->dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int sdw_fill_msg(struct sdw_msg *msg, struct sdw_slave *slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 addr, size_t count, u16 dev_num, u8 flags, u8 *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) memset(msg, 0, sizeof(*msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) msg->addr = addr; /* addr is 16 bit and truncated here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) msg->len = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) msg->dev_num = dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) msg->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) msg->buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (addr < SDW_REG_NO_PAGE) /* no paging area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (addr >= SDW_REG_MAX) { /* illegal addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pr_err("SDW: Invalid address %x passed\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (addr < SDW_REG_OPTIONAL_PAGE) { /* 32k but no page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (slave && !slave->prop.paging_support)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* no need for else as that will fall-through to paging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* paging mandatory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (dev_num == SDW_ENUM_DEV_NUM || dev_num == SDW_BROADCAST_DEV_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pr_err("SDW: Invalid device for paging :%d\n", dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pr_err("SDW: No slave for paging addr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!slave->prop.paging_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "address %x needs paging but no support\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msg->addr_page1 = FIELD_GET(SDW_SCP_ADDRPAGE1_MASK, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) msg->addr_page2 = FIELD_GET(SDW_SCP_ADDRPAGE2_MASK, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) msg->addr |= BIT(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) msg->page = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Read/Write IO functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * no_pm versions can only be called by the bus, e.g. while enumerating or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * handling suspend-resume sequences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * all clients need to use the pm versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) sdw_nread_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct sdw_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = sdw_fill_msg(&msg, slave, addr, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) slave->dev_num, SDW_MSG_FLAG_READ, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return sdw_transfer(slave->bus, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sdw_nwrite_no_pm(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct sdw_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = sdw_fill_msg(&msg, slave, addr, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) slave->dev_num, SDW_MSG_FLAG_WRITE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return sdw_transfer(slave->bus, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int sdw_write_no_pm(struct sdw_slave *slave, u32 addr, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return sdw_nwrite_no_pm(slave, addr, 1, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) EXPORT_SYMBOL(sdw_write_no_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) sdw_bread_no_pm(struct sdw_bus *bus, u16 dev_num, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct sdw_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) SDW_MSG_FLAG_READ, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = sdw_transfer(bus, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) sdw_bwrite_no_pm(struct sdw_bus *bus, u16 dev_num, u32 addr, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct sdw_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SDW_MSG_FLAG_WRITE, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return sdw_transfer(bus, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int sdw_bread_no_pm_unlocked(struct sdw_bus *bus, u16 dev_num, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct sdw_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SDW_MSG_FLAG_READ, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ret = sdw_transfer_unlocked(bus, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) EXPORT_SYMBOL(sdw_bread_no_pm_unlocked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int sdw_bwrite_no_pm_unlocked(struct sdw_bus *bus, u16 dev_num, u32 addr, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct sdw_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = sdw_fill_msg(&msg, NULL, addr, 1, dev_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) SDW_MSG_FLAG_WRITE, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return sdw_transfer_unlocked(bus, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) EXPORT_SYMBOL(sdw_bwrite_no_pm_unlocked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) int sdw_read_no_pm(struct sdw_slave *slave, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = sdw_nread_no_pm(slave, addr, 1, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) EXPORT_SYMBOL(sdw_read_no_pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int sdw_update_no_pm(struct sdw_slave *slave, u32 addr, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) tmp = sdw_read_no_pm(slave, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) tmp = (tmp & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return sdw_write_no_pm(slave, addr, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * sdw_nread() - Read "n" contiguous SDW Slave registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * @slave: SDW Slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * @addr: Register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * @count: length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * @val: Buffer for values to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = pm_runtime_get_sync(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ret < 0 && ret != -EACCES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pm_runtime_put_noidle(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = sdw_nread_no_pm(slave, addr, count, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pm_runtime_mark_last_busy(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pm_runtime_put(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) EXPORT_SYMBOL(sdw_nread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * sdw_nwrite() - Write "n" contiguous SDW Slave registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * @slave: SDW Slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * @addr: Register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * @count: length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * @val: Buffer for values to be read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = pm_runtime_get_sync(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret < 0 && ret != -EACCES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pm_runtime_put_noidle(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = sdw_nwrite_no_pm(slave, addr, count, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pm_runtime_mark_last_busy(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pm_runtime_put(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) EXPORT_SYMBOL(sdw_nwrite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * sdw_read() - Read a SDW Slave register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * @slave: SDW Slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * @addr: Register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int sdw_read(struct sdw_slave *slave, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u8 buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = sdw_nread(slave, addr, 1, &buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) EXPORT_SYMBOL(sdw_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * sdw_write() - Write a SDW Slave register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * @slave: SDW Slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * @addr: Register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * @value: Register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int sdw_write(struct sdw_slave *slave, u32 addr, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return sdw_nwrite(slave, addr, 1, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) EXPORT_SYMBOL(sdw_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * SDW alert handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* called with bus_lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static struct sdw_slave *sdw_get_slave(struct sdw_bus *bus, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct sdw_slave *slave = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) list_for_each_entry(slave, &bus->slaves, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (slave->dev_num == i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int sdw_compare_devid(struct sdw_slave *slave, struct sdw_slave_id id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (slave->id.mfg_id != id.mfg_id ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) slave->id.part_id != id.part_id ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) slave->id.class_id != id.class_id ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) (slave->id.unique_id != SDW_IGNORED_UNIQUE_ID &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) slave->id.unique_id != id.unique_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* called with bus_lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int sdw_get_device_num(struct sdw_slave *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) bit = find_first_zero_bit(slave->bus->assigned, SDW_MAX_DEVICES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (bit == SDW_MAX_DEVICES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) bit = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Do not update dev_num in Slave data structure here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * Update once program dev_num is successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) set_bit(bit, slave->bus->assigned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int sdw_assign_device_num(struct sdw_slave *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int ret, dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) bool new_device = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* check first if device number is assigned, if so reuse that */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!slave->dev_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!slave->dev_num_sticky) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mutex_lock(&slave->bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_num = sdw_get_device_num(slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mutex_unlock(&slave->bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (dev_num < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dev_err(slave->bus->dev, "Get dev_num failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) slave->dev_num = dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) slave->dev_num_sticky = dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) new_device = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) slave->dev_num = slave->dev_num_sticky;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!new_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) dev_dbg(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "Slave already registered, reusing dev_num:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) slave->dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* Clear the slave->dev_num to transfer message on device 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_num = slave->dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) slave->dev_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ret = sdw_write_no_pm(slave, SDW_SCP_DEVNUMBER, dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev_err(&slave->dev, "Program device_num %d failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) dev_num, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* After xfer of msg, restore dev_num */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) slave->dev_num = slave->dev_num_sticky;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) void sdw_extract_slave_id(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u64 addr, struct sdw_slave_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_dbg(bus->dev, "SDW Slave Addr: %llx\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) id->sdw_version = SDW_VERSION(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) id->unique_id = SDW_UNIQUE_ID(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) id->mfg_id = SDW_MFG_ID(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) id->part_id = SDW_PART_ID(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) id->class_id = SDW_CLASS_ID(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_dbg(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "SDW Slave class_id %x, part_id %x, mfg_id %x, unique_id %x, version %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) id->class_id, id->part_id, id->mfg_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) id->unique_id, id->sdw_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static int sdw_program_device_num(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u8 buf[SDW_NUM_DEV_ID_REGISTERS] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct sdw_slave *slave, *_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct sdw_slave_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct sdw_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) bool found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int count = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* No Slave, so use raw xfer api */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = sdw_fill_msg(&msg, NULL, SDW_SCP_DEVID_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) SDW_NUM_DEV_ID_REGISTERS, 0, SDW_MSG_FLAG_READ, buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ret = sdw_transfer(bus, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ret == -ENODATA) { /* end of device id reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_dbg(bus->dev, "No more devices to enumerate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_err(bus->dev, "DEVID read fail:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * Construct the addr and extract. Cast the higher shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * bits to avoid truncation due to size limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) addr = buf[5] | (buf[4] << 8) | (buf[3] << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ((u64)buf[2] << 24) | ((u64)buf[1] << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ((u64)buf[0] << 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) sdw_extract_slave_id(bus, addr, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* Now compare with entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) list_for_each_entry_safe(slave, _s, &bus->slaves, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (sdw_compare_devid(slave, id) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * Assign a new dev_num to this Slave and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * not mark it present. It will be marked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * present after it reports ATTACHED on new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * dev_num
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = sdw_assign_device_num(slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "Assign dev_num failed:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* TODO: Park this device in Group 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * add Slave device even if there is no platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * firmware description. There will be no driver probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * but the user/integration will be able to see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * device, enumeration status and device number in sysfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) sdw_slave_add(bus, &id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dev_err(bus->dev, "Slave Entry not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * Check till error out or retry (count) exhausts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * Device can drop off and rejoin during enumeration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * so count till twice the bound.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) } while (ret == 0 && count < (SDW_MAX_DEVICES * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static void sdw_modify_slave_status(struct sdw_slave *slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) enum sdw_slave_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mutex_lock(&slave->bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_vdbg(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "%s: changing status slave %d status %d new status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) __func__, slave->dev_num, slave->status, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (status == SDW_SLAVE_UNATTACHED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dev_dbg(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "%s: initializing completion for Slave %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) __func__, slave->dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) init_completion(&slave->enumeration_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) init_completion(&slave->initialization_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) } else if ((status == SDW_SLAVE_ATTACHED) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) (slave->status == SDW_SLAVE_UNATTACHED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_dbg(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "%s: signaling completion for Slave %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) __func__, slave->dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) complete(&slave->enumeration_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) slave->status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mutex_unlock(&slave->bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static enum sdw_clk_stop_mode sdw_get_clk_stop_mode(struct sdw_slave *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) enum sdw_clk_stop_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) * Query for clock stop mode if Slave implements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * ops->get_clk_stop_mode, else read from property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (slave->ops && slave->ops->get_clk_stop_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) mode = slave->ops->get_clk_stop_mode(slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (slave->prop.clk_stop_mode1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mode = SDW_CLK_STOP_MODE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mode = SDW_CLK_STOP_MODE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int sdw_slave_clk_stop_callback(struct sdw_slave *slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) enum sdw_clk_stop_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) enum sdw_clk_stop_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (slave->ops && slave->ops->clk_stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = slave->ops->clk_stop(slave, mode, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "Clk Stop type =%d failed: %d\n", type, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int sdw_slave_clk_stop_prepare(struct sdw_slave *slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) enum sdw_clk_stop_mode mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) bool prepare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) bool wake_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) wake_en = slave->prop.wake_capable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (prepare) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) val = SDW_SCP_SYSTEMCTRL_CLK_STP_PREP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (mode == SDW_CLK_STOP_MODE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) val |= SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (wake_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) val |= SDW_SCP_SYSTEMCTRL_WAKE_UP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) val = sdw_read_no_pm(slave, SDW_SCP_SYSTEMCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) val &= ~(SDW_SCP_SYSTEMCTRL_CLK_STP_PREP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret = sdw_write_no_pm(slave, SDW_SCP_SYSTEMCTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "Clock Stop prepare failed for slave: %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int sdw_bus_wait_for_clk_prep_deprep(struct sdw_bus *bus, u16 dev_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int retry = bus->clk_stop_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) val = sdw_bread_no_pm(bus, dev_num, SDW_SCP_STAT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) SDW_SCP_STAT_CLK_STP_NF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_info(bus->dev, "clock stop prep/de-prep done slave:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) usleep_range(1000, 1500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) retry--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) } while (retry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_err(bus->dev, "clock stop prep/de-prep failed slave:%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * sdw_bus_prep_clk_stop: prepare Slave(s) for clock stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * @bus: SDW bus instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * Query Slave for clock stop mode and prepare for that mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int sdw_bus_prep_clk_stop(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) enum sdw_clk_stop_mode slave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) bool simple_clk_stop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct sdw_slave *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) bool is_slave = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * In order to save on transition time, prepare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * each Slave and then wait for all Slave(s) to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * prepared for clock stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) list_for_each_entry(slave, &bus->slaves, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (!slave->dev_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (slave->status != SDW_SLAVE_ATTACHED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) slave->status != SDW_SLAVE_ALERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Identify if Slave(s) are available on Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) is_slave = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) slave_mode = sdw_get_clk_stop_mode(slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) slave->curr_clk_stop_mode = slave_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ret = sdw_slave_clk_stop_callback(slave, slave_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) SDW_CLK_PRE_PREPARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) "pre-prepare failed:%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ret = sdw_slave_clk_stop_prepare(slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) slave_mode, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) "pre-prepare failed:%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (slave_mode == SDW_CLK_STOP_MODE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) simple_clk_stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (is_slave && !simple_clk_stop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = sdw_bus_wait_for_clk_prep_deprep(bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) SDW_BROADCAST_DEV_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* Don't need to inform slaves if there is no slave attached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (!is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* Inform slaves that prep is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) list_for_each_entry(slave, &bus->slaves, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (!slave->dev_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (slave->status != SDW_SLAVE_ATTACHED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) slave->status != SDW_SLAVE_ALERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) slave_mode = slave->curr_clk_stop_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (slave_mode == SDW_CLK_STOP_MODE1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ret = sdw_slave_clk_stop_callback(slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) slave_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) SDW_CLK_POST_PREPARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) "post-prepare failed:%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) EXPORT_SYMBOL(sdw_bus_prep_clk_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * sdw_bus_clk_stop: stop bus clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * @bus: SDW bus instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * After preparing the Slaves for clock stop, stop the clock by broadcasting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * write to SCP_CTRL register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) int sdw_bus_clk_stop(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * broadcast clock stop now, attached Slaves will ACK this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * unattached will ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = sdw_bwrite_no_pm(bus, SDW_BROADCAST_DEV_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) SDW_SCP_CTRL, SDW_SCP_CTRL_CLK_STP_NOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (ret == -ENODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dev_dbg(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) "ClockStopNow Broadcast msg ignored %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "ClockStopNow Broadcast msg failed %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) EXPORT_SYMBOL(sdw_bus_clk_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * sdw_bus_exit_clk_stop: Exit clock stop mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * @bus: SDW bus instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * This De-prepares the Slaves by exiting Clock Stop Mode 0. For the Slaves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * exiting Clock Stop Mode 1, they will be de-prepared after they enumerate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) int sdw_bus_exit_clk_stop(struct sdw_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) enum sdw_clk_stop_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) bool simple_clk_stop = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct sdw_slave *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) bool is_slave = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * In order to save on transition time, de-prepare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * each Slave and then wait for all Slave(s) to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * de-prepared after clock resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) list_for_each_entry(slave, &bus->slaves, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (!slave->dev_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (slave->status != SDW_SLAVE_ATTACHED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) slave->status != SDW_SLAVE_ALERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Identify if Slave(s) are available on Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) is_slave = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) mode = slave->curr_clk_stop_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (mode == SDW_CLK_STOP_MODE1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) simple_clk_stop = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ret = sdw_slave_clk_stop_callback(slave, mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) SDW_CLK_PRE_DEPREPARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev_warn(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "clk stop deprep failed:%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = sdw_slave_clk_stop_prepare(slave, mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_warn(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "clk stop deprep failed:%d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (is_slave && !simple_clk_stop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) sdw_bus_wait_for_clk_prep_deprep(bus, SDW_BROADCAST_DEV_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * Don't need to call slave callback function if there is no slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (!is_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) list_for_each_entry(slave, &bus->slaves, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (!slave->dev_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (slave->status != SDW_SLAVE_ATTACHED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) slave->status != SDW_SLAVE_ALERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) mode = slave->curr_clk_stop_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) sdw_slave_clk_stop_callback(slave, mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) SDW_CLK_POST_DEPREPARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) EXPORT_SYMBOL(sdw_bus_exit_clk_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) int sdw_configure_dpn_intr(struct sdw_slave *slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int port, bool enable, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (slave->bus->params.s_data_mode != SDW_PORT_DATA_MODE_NORMAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dev_dbg(&slave->dev, "TEST FAIL interrupt %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) enable ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mask |= SDW_DPN_INT_TEST_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) addr = SDW_DPN_INTMASK(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Set/Clear port ready interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) val |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) val |= SDW_DPN_INT_PORT_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) val &= ~(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) val &= ~SDW_DPN_INT_PORT_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ret = sdw_update(slave, addr, (mask | SDW_DPN_INT_PORT_READY), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) "SDW_DPN_INTMASK write failed:%d\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static int sdw_slave_set_frequency(struct sdw_slave *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) u32 mclk_freq = slave->bus->prop.mclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 curr_freq = slave->bus->params.curr_dr_freq >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) unsigned int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) u8 scale_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * frequency base and scale registers are required for SDCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * devices. They may also be used for 1.2+/non-SDCA devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * but we will need a DisCo property to cover this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (!slave->id.class_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (!mclk_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) "no bus MCLK, cannot set SDW_SCP_BUS_CLOCK_BASE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * map base frequency using Table 89 of SoundWire 1.2 spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * The order of the tests just follows the specification, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * is not a selection between possible values or a search for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * the best value but just a mapping. Only one case per platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * is relevant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * Some BIOS have inconsistent values for mclk_freq but a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * correct root so we force the mclk_freq to avoid variations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (!(19200000 % mclk_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) mclk_freq = 19200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) base = SDW_SCP_BASE_CLOCK_19200000_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) } else if (!(24000000 % mclk_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) mclk_freq = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) base = SDW_SCP_BASE_CLOCK_24000000_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) } else if (!(24576000 % mclk_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) mclk_freq = 24576000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) base = SDW_SCP_BASE_CLOCK_24576000_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) } else if (!(22579200 % mclk_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) mclk_freq = 22579200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) base = SDW_SCP_BASE_CLOCK_22579200_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) } else if (!(32000000 % mclk_freq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) mclk_freq = 32000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) base = SDW_SCP_BASE_CLOCK_32000000_HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "Unsupported clock base, mclk %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) mclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (mclk_freq % curr_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) "mclk %d is not multiple of bus curr_freq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mclk_freq, curr_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) scale = mclk_freq / curr_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * map scale to Table 90 of SoundWire 1.2 spec - and check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * that the scale is a power of two and maximum 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) scale_index = ilog2(scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (BIT(scale_index) != scale || scale_index > 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) "No match found for scale %d, bus mclk %d curr_freq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) scale, mclk_freq, curr_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) scale_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ret = sdw_write_no_pm(slave, SDW_SCP_BUS_CLOCK_BASE, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) "SDW_SCP_BUS_CLOCK_BASE write failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* initialize scale for both banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ret = sdw_write_no_pm(slave, SDW_SCP_BUSCLOCK_SCALE_B0, scale_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) "SDW_SCP_BUSCLOCK_SCALE_B0 write failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ret = sdw_write_no_pm(slave, SDW_SCP_BUSCLOCK_SCALE_B1, scale_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_err(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) "SDW_SCP_BUSCLOCK_SCALE_B1 write failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) dev_dbg(&slave->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) "Configured bus base %d, scale %d, mclk %d, curr_freq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) base, scale_index, mclk_freq, curr_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static int sdw_initialize_slave(struct sdw_slave *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct sdw_slave_prop *prop = &slave->prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = sdw_slave_set_frequency(slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * Set SCP_INT1_MASK register, typically bus clash and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * implementation-defined interrupt mask. The Parity detection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * may not always be correct on startup so its use is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * device-dependent, it might e.g. only be enabled in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) * steady-state after a couple of frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) val = slave->prop.scp_int1_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* Enable SCP interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = sdw_update_no_pm(slave, SDW_SCP_INTMASK1, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) "SDW_SCP_INTMASK1 write failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* No need to continue if DP0 is not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (!slave->prop.dp0_prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* Enable DP0 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) val = prop->dp0_prop->imp_def_interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) val |= SDW_DP0_INT_PORT_READY | SDW_DP0_INT_BRA_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ret = sdw_update_no_pm(slave, SDW_DP0_INTMASK, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) "SDW_DP0_INTMASK read failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static int sdw_handle_dp0_interrupt(struct sdw_slave *slave, u8 *slave_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) u8 clear = 0, impl_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) int status, status2, ret, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) status = sdw_read(slave, SDW_DP0_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) "SDW_DP0_INT read failed:%d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (status & SDW_DP0_INT_TEST_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) dev_err(&slave->dev, "Test fail for port 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) clear |= SDW_DP0_INT_TEST_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * Assumption: PORT_READY interrupt will be received only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * ports implementing Channel Prepare state machine (CP_SM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (status & SDW_DP0_INT_PORT_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) complete(&slave->port_ready[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) clear |= SDW_DP0_INT_PORT_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (status & SDW_DP0_INT_BRA_FAILURE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_err(&slave->dev, "BRA failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) clear |= SDW_DP0_INT_BRA_FAILURE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) impl_int_mask = SDW_DP0_INT_IMPDEF1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) SDW_DP0_INT_IMPDEF2 | SDW_DP0_INT_IMPDEF3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (status & impl_int_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) clear |= impl_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) *slave_status = clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret = sdw_write(slave, SDW_DP0_INT, clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) "SDW_DP0_INT write failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* Read DP0 interrupt again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) status2 = sdw_read(slave, SDW_DP0_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (status2 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) "SDW_DP0_INT read failed:%d\n", status2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) status &= status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* we can get alerts while processing so keep retrying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) } while (status != 0 && count < SDW_READ_INTR_CLEAR_RETRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (count == SDW_READ_INTR_CLEAR_RETRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) dev_warn(slave->bus->dev, "Reached MAX_RETRY on DP0 read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static int sdw_handle_port_interrupt(struct sdw_slave *slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) int port, u8 *slave_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) u8 clear = 0, impl_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) int status, status2, ret, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (port == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return sdw_handle_dp0_interrupt(slave, slave_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) addr = SDW_DPN_INT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) status = sdw_read(slave, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (status < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) "SDW_DPN_INT read failed:%d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (status & SDW_DPN_INT_TEST_FAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dev_err(&slave->dev, "Test fail for port:%d\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) clear |= SDW_DPN_INT_TEST_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * Assumption: PORT_READY interrupt will be received only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * for ports implementing CP_SM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (status & SDW_DPN_INT_PORT_READY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) complete(&slave->port_ready[port]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) clear |= SDW_DPN_INT_PORT_READY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) impl_int_mask = SDW_DPN_INT_IMPDEF1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) SDW_DPN_INT_IMPDEF2 | SDW_DPN_INT_IMPDEF3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (status & impl_int_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) clear |= impl_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) *slave_status = clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* clear the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) ret = sdw_write(slave, addr, clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) "SDW_DPN_INT write failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* Read DPN interrupt again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) status2 = sdw_read(slave, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (status2 < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) "SDW_DPN_INT read failed:%d\n", status2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) return status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) status &= status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /* we can get alerts while processing so keep retrying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) } while (status != 0 && count < SDW_READ_INTR_CLEAR_RETRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (count == SDW_READ_INTR_CLEAR_RETRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dev_warn(slave->bus->dev, "Reached MAX_RETRY on port read");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static int sdw_handle_slave_alerts(struct sdw_slave *slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) struct sdw_slave_intr_status slave_intr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) u8 clear = 0, bit, port_status[15] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) int port_num, stat, ret, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) unsigned long port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) bool slave_notify = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u8 buf, buf2[2], _buf, _buf2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) bool parity_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) bool parity_quirk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) sdw_modify_slave_status(slave, SDW_SLAVE_ALERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ret = pm_runtime_get_sync(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (ret < 0 && ret != -EACCES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) dev_err(&slave->dev, "Failed to resume device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) pm_runtime_put_noidle(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* Read Intstat 1, Intstat 2 and Intstat 3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) ret = sdw_read(slave, SDW_SCP_INT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) "SDW_SCP_INT1 read failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) goto io_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) buf = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ret = sdw_nread(slave, SDW_SCP_INTSTAT2, 2, buf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) "SDW_SCP_INT2/3 read failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) goto io_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) * Check parity, bus clash and Slave (impl defined)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) * interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (buf & SDW_SCP_INT1_PARITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) parity_check = slave->prop.scp_int1_mask & SDW_SCP_INT1_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) parity_quirk = !slave->first_interrupt_done &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) (slave->prop.quirks & SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (parity_check && !parity_quirk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) dev_err(&slave->dev, "Parity error detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) clear |= SDW_SCP_INT1_PARITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (buf & SDW_SCP_INT1_BUS_CLASH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (slave->prop.scp_int1_mask & SDW_SCP_INT1_BUS_CLASH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) dev_err(&slave->dev, "Bus clash detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) clear |= SDW_SCP_INT1_BUS_CLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) * When bus clash or parity errors are detected, such errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) * are unlikely to be recoverable errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * TODO: In such scenario, reset bus. Make this configurable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * via sysfs property with bus reset being the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (buf & SDW_SCP_INT1_IMPL_DEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (slave->prop.scp_int1_mask & SDW_SCP_INT1_IMPL_DEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_dbg(&slave->dev, "Slave impl defined interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) slave_notify = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) clear |= SDW_SCP_INT1_IMPL_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* Check port 0 - 3 interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) port = buf & SDW_SCP_INT1_PORT0_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* To get port number corresponding to bits, shift it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) port = FIELD_GET(SDW_SCP_INT1_PORT0_3, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) for_each_set_bit(bit, &port, 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) sdw_handle_port_interrupt(slave, bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) &port_status[bit]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* Check if cascade 2 interrupt is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (buf & SDW_SCP_INT1_SCP2_CASCADE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) port = buf2[0] & SDW_SCP_INTSTAT2_PORT4_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) for_each_set_bit(bit, &port, 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* scp2 ports start from 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) port_num = bit + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) sdw_handle_port_interrupt(slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) &port_status[port_num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* now check last cascade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (buf2[0] & SDW_SCP_INTSTAT2_SCP3_CASCADE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) port = buf2[1] & SDW_SCP_INTSTAT3_PORT11_14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) for_each_set_bit(bit, &port, 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* scp3 ports start from 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) port_num = bit + 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) sdw_handle_port_interrupt(slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) port_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) &port_status[port_num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* Update the Slave driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (slave_notify && slave->ops &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) slave->ops->interrupt_callback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) slave_intr.control_port = clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) memcpy(slave_intr.port, &port_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) sizeof(slave_intr.port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) slave->ops->interrupt_callback(slave, &slave_intr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* Ack interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) ret = sdw_write(slave, SDW_SCP_INT1, clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) "SDW_SCP_INT1 write failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) goto io_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* at this point all initial interrupt sources were handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) slave->first_interrupt_done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) * Read status again to ensure no new interrupts arrived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) * while servicing interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ret = sdw_read(slave, SDW_SCP_INT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) "SDW_SCP_INT1 read failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) goto io_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) _buf = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) ret = sdw_nread(slave, SDW_SCP_INTSTAT2, 2, _buf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) "SDW_SCP_INT2/3 read failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) goto io_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /* Make sure no interrupts are pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) buf &= _buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) buf2[0] &= _buf2[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) buf2[1] &= _buf2[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) stat = buf || buf2[0] || buf2[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) * Exit loop if Slave is continuously in ALERT state even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) * after servicing the interrupt multiple times.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* we can get alerts while processing so keep retrying */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) } while (stat != 0 && count < SDW_READ_INTR_CLEAR_RETRY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (count == SDW_READ_INTR_CLEAR_RETRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dev_warn(slave->bus->dev, "Reached MAX_RETRY on alert read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) io_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) pm_runtime_mark_last_busy(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pm_runtime_put_autosuspend(&slave->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static int sdw_update_slave_status(struct sdw_slave *slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) enum sdw_slave_status status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) unsigned long time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (!slave->probed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) * the slave status update is typically handled in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * interrupt thread, which can race with the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * probe, e.g. when a module needs to be loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * make sure the probe is complete before updating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) * status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) time = wait_for_completion_timeout(&slave->probe_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) msecs_to_jiffies(DEFAULT_PROBE_TIMEOUT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) if (!time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) dev_err(&slave->dev, "Probe not complete, timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (!slave->ops || !slave->ops->update_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return slave->ops->update_status(slave, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * sdw_handle_slave_status() - Handle Slave status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) * @bus: SDW bus instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) * @status: Status for all Slave(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) int sdw_handle_slave_status(struct sdw_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) enum sdw_slave_status status[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) enum sdw_slave_status prev_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct sdw_slave *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) bool attached_initializing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /* first check if any Slaves fell off the bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) for (i = 1; i <= SDW_MAX_DEVICES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) mutex_lock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (test_bit(i, bus->assigned) == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) mutex_unlock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) mutex_unlock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) slave = sdw_get_slave(bus, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (!slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (status[i] == SDW_SLAVE_UNATTACHED &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) slave->status != SDW_SLAVE_UNATTACHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (status[0] == SDW_SLAVE_ATTACHED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) dev_dbg(bus->dev, "Slave attached, programming device number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) ret = sdw_program_device_num(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) dev_err(bus->dev, "Slave attach failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) * programming a device number will have side effects,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) * so we deal with other devices at a later time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* Continue to check other slave statuses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) for (i = 1; i <= SDW_MAX_DEVICES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) mutex_lock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (test_bit(i, bus->assigned) == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) mutex_unlock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) mutex_unlock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) slave = sdw_get_slave(bus, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (!slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) attached_initializing = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) switch (status[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) case SDW_SLAVE_UNATTACHED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (slave->status == SDW_SLAVE_UNATTACHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) case SDW_SLAVE_ALERT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ret = sdw_handle_slave_alerts(slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) "Slave %d alert handling failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) case SDW_SLAVE_ATTACHED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) if (slave->status == SDW_SLAVE_ATTACHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) prev_status = slave->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) sdw_modify_slave_status(slave, SDW_SLAVE_ATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (prev_status == SDW_SLAVE_ALERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) attached_initializing = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) ret = sdw_initialize_slave(slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) dev_err(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) "Slave %d initialization failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) dev_err(bus->dev, "Invalid slave %d status:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) i, status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ret = sdw_update_slave_status(slave, status[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) dev_err(slave->bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) "Update Slave status failed:%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (attached_initializing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) complete(&slave->initialization_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) EXPORT_SYMBOL(sdw_handle_slave_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) void sdw_clear_slave_status(struct sdw_bus *bus, u32 request)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct sdw_slave *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* Check all non-zero devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) for (i = 1; i <= SDW_MAX_DEVICES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) mutex_lock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (test_bit(i, bus->assigned) == false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) mutex_unlock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) mutex_unlock(&bus->bus_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) slave = sdw_get_slave(bus, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (!slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (slave->status != SDW_SLAVE_UNATTACHED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) sdw_modify_slave_status(slave, SDW_SLAVE_UNATTACHED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) slave->first_interrupt_done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) /* keep track of request, used in pm_runtime resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) slave->unattach_request = request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) EXPORT_SYMBOL(sdw_clear_slave_status);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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