^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define INTEGRATOR_HDR_ID_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static u32 integrator_coreid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct of_device_id integrator_cm_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { .compatible = "arm,core-module-integrator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const char *integrator_arch_str(u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) switch ((id >> 16) & 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) case 0x00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return "ASB little-endian";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return "AHB little-endian";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return "AHB-Lite system bus, bi-endian";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return "AHB";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) case 0x08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return "AHB system bus, ASB processor bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const char *integrator_fpga_str(u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) switch ((id >> 12) & 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) case 0x01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return "XC4062";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return "XC4085";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case 0x03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return "XVC600";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return "EPM7256AE (Altera PLD)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) manufacturer_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return sprintf(buf, "%02x\n", integrator_coreid >> 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static DEVICE_ATTR_RO(manufacturer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) arch_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return sprintf(buf, "%s\n", integrator_arch_str(integrator_coreid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static DEVICE_ATTR_RO(arch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) fpga_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return sprintf(buf, "%s\n", integrator_fpga_str(integrator_coreid));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static DEVICE_ATTR_RO(fpga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) build_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return sprintf(buf, "%02x\n", (integrator_coreid >> 4) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static DEVICE_ATTR_RO(build);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct attribute *integrator_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) &dev_attr_manufacturer.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &dev_attr_arch.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) &dev_attr_fpga.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) &dev_attr_build.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ATTRIBUTE_GROUPS(integrator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int __init integrator_soc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct regmap *syscon_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct soc_device *soc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct soc_device_attribute *soc_dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) np = of_find_matching_node(NULL, integrator_cm_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) syscon_regmap = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (IS_ERR(syscon_regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return PTR_ERR(syscon_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = regmap_read(syscon_regmap, INTEGRATOR_HDR_ID_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) integrator_coreid = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!soc_dev_attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) soc_dev_attr->soc_id = "Integrator";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) soc_dev_attr->machine = "Integrator";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) soc_dev_attr->family = "Versatile";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) soc_dev_attr->custom_attr_group = integrator_groups[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) soc_dev = soc_device_register(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (IS_ERR(soc_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) kfree(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev = soc_device_to_device(soc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dev_info(dev, "Detected ARM core module:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_info(dev, " Manufacturer: %02x\n", (val >> 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_info(dev, " Architecture: %s\n", integrator_arch_str(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dev_info(dev, " FPGA: %s\n", integrator_fpga_str(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_info(dev, " Build: %02x\n", (val >> 4) & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_info(dev, " Rev: %c\n", ('A' + (val & 0x03)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) device_initcall(integrator_soc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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