^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OMAP2+ PRM driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Tero Kristo <t-kristo@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_data/ti-prm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum omap_prm_domain_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) OMAP_PRMD_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) OMAP_PRMD_RETENTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) OMAP_PRMD_ON_INACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) OMAP_PRMD_ON_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct omap_prm_domain_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int usable_modes; /* Mask of hardware supported modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long statechange:1; /* Optional low-power state change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long logicretstate:1; /* Optional logic off mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct omap_prm_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct omap_prm *prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct generic_pm_domain pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u16 pwrstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u16 pwrstst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const struct omap_prm_domain_map *cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 pwrstctrl_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct omap_rst_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) s8 rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) s8 st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct omap_prm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const char *clkdm_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u16 pwrstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 pwrstst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct omap_prm_domain_map *dmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 rstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 rstst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct omap_rst_map *rstmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct omap_prm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const struct omap_prm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct omap_prm_domain *prmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct omap_reset_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct omap_prm *prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clockdomain *clkdm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define genpd_to_prm_domain(gpd) container_of(gpd, struct omap_prm_domain, pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OMAP_MAX_RESETS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OMAP_RESET_MAX_WAIT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OMAP_PRM_HAS_RSTCTRL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OMAP_PRM_HAS_RSTST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OMAP_PRM_HAS_NO_CLKDM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PRM_STATE_MAX_WAIT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PRM_LOGICRETSTATE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PRM_LOWPOWERSTATECHANGE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PRM_POWERSTATE_MASK OMAP_PRMD_ON_ACTIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PRM_ST_INTRANSITION BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct omap_prm_domain_map omap_prm_all = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_ON_INACTIVE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) BIT(OMAP_PRMD_RETENTION) | BIT(OMAP_PRMD_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .statechange = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .logicretstate = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct omap_prm_domain_map omap_prm_noinact = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_RETENTION) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) BIT(OMAP_PRMD_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .statechange = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .logicretstate = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct omap_prm_domain_map omap_prm_nooff = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_ON_INACTIVE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) BIT(OMAP_PRMD_RETENTION),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .statechange = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .logicretstate = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct omap_prm_domain_map omap_prm_onoff_noauto = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .statechange = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct omap_rst_map rst_map_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { .rst = 0, .st = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .rst = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct omap_rst_map rst_map_01[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .rst = 0, .st = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .rst = 1, .st = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { .rst = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct omap_rst_map rst_map_012[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { .rst = 0, .st = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .rst = 1, .st = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .rst = 2, .st = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .rst = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const struct omap_prm_data omap4_prm_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .name = "tesla", .base = 0x4a306400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "abe", .base = 0x4a306500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .name = "core", .base = 0x4a306700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati", .rstmap = rst_map_012 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .name = "ivahd", .base = 0x4a306f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { .name = "device", .base = 0x4a307b00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct omap_prm_data omap5_prm_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .name = "dsp", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "abe", .base = 0x4ae06500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_nooff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu", .rstmap = rst_map_012 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { .name = "iva", .base = 0x4ae07200, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { .name = "device", .base = 0x4ae07c00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct omap_prm_data dra7_prm_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2", .rstmap = rst_map_012 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .name = "iva", .base = 0x4ae06f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .name = "dsp2", .base = 0x4ae07b00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .name = "eve1", .base = 0x4ae07b40, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { .name = "eve2", .base = 0x4ae07b80, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .name = "eve3", .base = 0x4ae07bc0, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .name = "eve4", .base = 0x4ae07c00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct omap_rst_map am3_per_rst_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .rst = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .rst = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct omap_rst_map am3_wkup_rst_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .rst = 3, .st = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .rst = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct omap_prm_data am3_prm_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .name = "per", .base = 0x44e00c00, .rstctrl = 0x0, .rstmap = am3_per_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL, .clkdm_name = "pruss_ocp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .name = "wkup", .base = 0x44e00d00, .rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .name = "device", .base = 0x44e00f00, .rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "gfx", .base = 0x44e01100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .pwrstctrl = 0, .pwrstst = 0x10, .dmap = &omap_prm_noinact,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct omap_rst_map am4_per_rst_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .rst = 1, .st = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .rst = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct omap_rst_map am4_device_rst_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .rst = 0, .st = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .rst = 1, .st = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .rst = -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct omap_prm_data am4_prm_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = "gfx", .base = 0x44df0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .pwrstctrl = 0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { .name = "per", .base = 0x44df0800, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map, .clkdm_name = "pruss_ocp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { .name = "wkup", .base = 0x44df2000, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_NO_CLKDM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { .name = "device", .base = 0x44df4000, .rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct of_device_id omap_prm_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { .compatible = "ti,omap5-prm-inst", .data = omap5_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { .compatible = "ti,am3-prm-inst", .data = am3_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { .compatible = "ti,am4-prm-inst", .data = am4_prm_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void omap_prm_domain_show_state(struct omap_prm_domain *prmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) const char *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_dbg(prmd->dev, "%s %s: %08x/%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) prmd->pd.name, desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) readl_relaxed(prmd->prm->base + prmd->pwrstctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) readl_relaxed(prmd->prm->base + prmd->pwrstst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline void omap_prm_domain_show_state(struct omap_prm_domain *prmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) const char *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int omap_prm_domain_power_on(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct omap_prm_domain *prmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) prmd = genpd_to_prm_domain(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!prmd->cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) omap_prm_domain_show_state(prmd, "on: previous state");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (prmd->pwrstctrl_saved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) v = prmd->pwrstctrl_saved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel_relaxed(v | OMAP_PRMD_ON_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) prmd->prm->base + prmd->pwrstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* wait for the transition bit to get cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = readl_relaxed_poll_timeout(prmd->prm->base + prmd->pwrstst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) v, !(v & PRM_ST_INTRANSITION), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PRM_STATE_MAX_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_err(prmd->dev, "%s: %s timed out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) prmd->pd.name, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) omap_prm_domain_show_state(prmd, "on: new state");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* No need to check for holes in the mask for the lowest mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int omap_prm_domain_find_lowest(struct omap_prm_domain *prmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return __ffs(prmd->cap->usable_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int omap_prm_domain_power_off(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct omap_prm_domain *prmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) prmd = genpd_to_prm_domain(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!prmd->cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) omap_prm_domain_show_state(prmd, "off: previous state");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) v = readl_relaxed(prmd->prm->base + prmd->pwrstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) prmd->pwrstctrl_saved = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) v &= ~PRM_POWERSTATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) v |= omap_prm_domain_find_lowest(prmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (prmd->cap->statechange)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) v |= PRM_LOWPOWERSTATECHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (prmd->cap->logicretstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) v &= ~PRM_LOGICRETSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) v |= PRM_LOGICRETSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writel_relaxed(v, prmd->prm->base + prmd->pwrstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* wait for the transition bit to get cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ret = readl_relaxed_poll_timeout(prmd->prm->base + prmd->pwrstst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) v, !(v & PRM_ST_INTRANSITION), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PRM_STATE_MAX_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_warn(prmd->dev, "%s: %s timed out\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __func__, prmd->pd.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) omap_prm_domain_show_state(prmd, "off: new state");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int omap_prm_domain_attach_dev(struct generic_pm_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct generic_pm_domain_data *genpd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct of_phandle_args pd_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct omap_prm_domain *prmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) prmd = genpd_to_prm_domain(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = of_parse_phandle_with_args(np, "power-domains",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "#power-domain-cells", 0, &pd_args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (pd_args.args_count != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_warn(dev, "%s: unusupported #power-domain-cells: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) prmd->pd.name, pd_args.args_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) genpd_data = dev_gpd_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) genpd_data->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static void omap_prm_domain_detach_dev(struct generic_pm_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct generic_pm_domain_data *genpd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) genpd_data = dev_gpd_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) genpd_data->data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int omap_prm_domain_init(struct device *dev, struct omap_prm *prm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct omap_prm_domain *prmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) const struct omap_prm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!of_find_property(dev->of_node, "#power-domain-cells", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) of_node_put(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) prmd = devm_kzalloc(dev, sizeof(*prmd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (!prmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) data = prm->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) name = devm_kasprintf(dev, GFP_KERNEL, "prm_%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) prmd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) prmd->prm = prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) prmd->cap = prmd->prm->data->dmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) prmd->pwrstctrl = prmd->prm->data->pwrstctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) prmd->pwrstst = prmd->prm->data->pwrstst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) prmd->pd.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) prmd->pd.power_on = omap_prm_domain_power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) prmd->pd.power_off = omap_prm_domain_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) prmd->pd.attach_dev = omap_prm_domain_attach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) prmd->pd.detach_dev = omap_prm_domain_detach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pm_genpd_init(&prmd->pd, NULL, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) error = of_genpd_add_provider_simple(np, &prmd->pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pm_genpd_remove(&prmd->pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) prm->prmd = prmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (reset->mask & BIT(id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int omap_reset_get_st_bit(struct omap_reset_data *reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) const struct omap_rst_map *map = reset->prm->data->rstmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) while (map->rst >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (map->rst == id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return map->st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static int omap_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct omap_reset_data *reset = to_omap_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int st_bit = omap_reset_get_st_bit(reset, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) bool has_rstst = reset->prm->data->rstst ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) (reset->prm->data->flags & OMAP_PRM_HAS_RSTST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Check if we have rstst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!has_rstst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Check if hw reset line is asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (v & BIT(id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * Check reset status, high value means reset sequence has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * completed successfully so we can return 0 here (reset deasserted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) v = readl_relaxed(reset->prm->base + reset->prm->data->rstst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) v >>= st_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) v &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return !v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static int omap_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct omap_reset_data *reset = to_omap_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* assert the reset control line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) spin_lock_irqsave(&reset->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) v |= 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) spin_unlock_irqrestore(&reset->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int omap_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct omap_reset_data *reset = to_omap_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int st_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) bool has_rstst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Nothing to do if the reset is already deasserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!omap_reset_status(rcdev, id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) has_rstst = reset->prm->data->rstst ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) (reset->prm->data->flags & OMAP_PRM_HAS_RSTST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (has_rstst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) st_bit = omap_reset_get_st_bit(reset, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Clear the reset status by writing 1 to the status bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) v = 1 << st_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) writel_relaxed(v, reset->prm->base + reset->prm->data->rstst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (reset->clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pdata->clkdm_deny_idle(reset->clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* de-assert the reset control line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) spin_lock_irqsave(&reset->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) v &= ~(1 << id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) spin_unlock_irqrestore(&reset->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* wait for the reset bit to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = readl_relaxed_poll_timeout_atomic(reset->prm->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) reset->prm->data->rstctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) v, !(v & BIT(id)), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) OMAP_RESET_MAX_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pr_err("%s: timedout waiting for %s:%lu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) reset->prm->data->name, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* wait for the status to be set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (has_rstst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = readl_relaxed_poll_timeout_atomic(reset->prm->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) reset->prm->data->rstst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) v, v & BIT(st_bit), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) OMAP_RESET_MAX_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pr_err("%s: timedout waiting for %s:%lu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) reset->prm->data->name, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (reset->clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pdata->clkdm_allow_idle(reset->clkdm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const struct reset_control_ops omap_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .assert = omap_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .deassert = omap_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .status = omap_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int omap_prm_reset_xlate(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) const struct of_phandle_args *reset_spec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct omap_reset_data *reset = to_omap_reset_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!_is_valid_reset(reset, reset_spec->args[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return reset_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int omap_prm_reset_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct omap_prm *prm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct omap_reset_data *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) const struct omap_rst_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) char buf[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * Check if we have controllable resets. If either rstctrl is non-zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * or OMAP_PRM_HAS_RSTCTRL flag is set, we have reset control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * for the domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Check if we have the pdata callbacks in place */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!pdata || !pdata->clkdm_lookup || !pdata->clkdm_deny_idle ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) !pdata->clkdm_allow_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) map = prm->data->rstmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (!reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) reset->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) reset->rcdev.ops = &omap_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) reset->rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) reset->rcdev.nr_resets = OMAP_MAX_RESETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) reset->rcdev.of_xlate = omap_prm_reset_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) reset->rcdev.of_reset_n_cells = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) reset->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) spin_lock_init(&reset->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) reset->prm = prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) prm->data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!(prm->data->flags & OMAP_PRM_HAS_NO_CLKDM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) reset->clkdm = pdata->clkdm_lookup(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!reset->clkdm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) while (map->rst >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) reset->mask |= BIT(map->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Quirk handling to assert rst_map_012 bits on reset and avoid errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (prm->data->rstmap == rst_map_012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if ((v & reset->mask) != reset->mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_dbg(&pdev->dev, "Asserting all resets: %08x\n", v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) writel_relaxed(reset->mask, reset->prm->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) reset->prm->data->rstctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int omap_prm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) const struct omap_prm_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct omap_prm *prm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) match = of_match_device(omap_prm_id_table, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) prm = devm_kzalloc(&pdev->dev, sizeof(*prm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!prm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) while (data->base != res->start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!data->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) data++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) prm->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) prm->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (IS_ERR(prm->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return PTR_ERR(prm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = omap_prm_domain_init(&pdev->dev, prm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = omap_prm_reset_init(pdev, prm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) goto err_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) err_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) of_genpd_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pm_genpd_remove(&prm->prmd->pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static struct platform_driver omap_prm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .probe = omap_prm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .of_match_table = omap_prm_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) builtin_platform_driver(omap_prm_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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