^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Authors: Santosh Shilimkar <santosh.shilimkar@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Sandeep Nair <sandeep_n@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Cyril Chemparathy <cyril@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dma-direction.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/soc/ti/knav_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DMA_LOOPBACK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DMA_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMA_TEARDOWN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMA_TX_FILT_PSWORDS BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMA_TX_FILT_EINFO BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DMA_TX_PRIO_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DMA_RX_PRIO_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMA_PRIO_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DMA_PRIO_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DMA_RX_TIMEOUT_DEFAULT 17500 /* cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DMA_RX_TIMEOUT_MASK GENMASK(16, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DMA_RX_TIMEOUT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHAN_HAS_EPIB BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHAN_HAS_PSINFO BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CHAN_ERR_RETRY BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CHAN_PSINFO_AT_SOP BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CHAN_SOP_OFF_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CHAN_SOP_OFF_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DESC_TYPE_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DESC_TYPE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * QMGR & QNUM together make up 14 bits with QMGR as the 2 MSb's in the logical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * navigator cloud mapping scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * using the 14bit physical queue numbers directly maps into this scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CHAN_QNUM_MASK GENMASK(14, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DMA_MAX_QMS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DMA_TIMEOUT 1 /* msecs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DMA_INVALID_ID 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct reg_global {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 perf_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 emulation_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 priority_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 qm_base_address[DMA_MAX_QMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct reg_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 __rsvd[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct reg_tx_sched {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct reg_rx_flow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 tags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 tag_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 fdq_sel[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 thresh[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct knav_dma_pool_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct knav_dma_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool loopback, enable_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned tx_priority, rx_priority, rx_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned logical_queue_managers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned qm_base_address[DMA_MAX_QMS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct reg_global __iomem *reg_global;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct reg_chan __iomem *reg_tx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct reg_rx_flow __iomem *reg_rx_flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct reg_chan __iomem *reg_rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct reg_tx_sched __iomem *reg_tx_sched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned max_rx_chan, max_tx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned max_rx_flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) atomic_t ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct list_head chan_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct knav_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct knav_dma_device *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) atomic_t ref_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct reg_chan __iomem *reg_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct reg_tx_sched __iomem *reg_tx_sched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct reg_rx_flow __iomem *reg_rx_flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* configuration stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned channel, flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct knav_dma_cfg cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define chan_number(ch) ((ch->direction == DMA_MEM_TO_DEV) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ch->channel : ch->flow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static struct knav_dma_pool_device *kdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static bool device_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool knav_dma_device_ready(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return device_ready;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) EXPORT_SYMBOL_GPL(knav_dma_device_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static bool check_config(struct knav_dma_chan *chan, struct knav_dma_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!memcmp(&chan->cfg, cfg, sizeof(*cfg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int chan_start(struct knav_dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct knav_dma_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) spin_lock(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if ((chan->direction == DMA_MEM_TO_DEV) && chan->reg_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (cfg->u.tx.filt_pswords)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) v |= DMA_TX_FILT_PSWORDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (cfg->u.tx.filt_einfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) v |= DMA_TX_FILT_EINFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) writel_relaxed(v, &chan->reg_chan->mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel_relaxed(DMA_ENABLE, &chan->reg_chan->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (chan->reg_tx_sched)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writel_relaxed(cfg->u.tx.priority, &chan->reg_tx_sched->prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (chan->reg_rx_flow) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (cfg->u.rx.einfo_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) v |= CHAN_HAS_EPIB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (cfg->u.rx.psinfo_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) v |= CHAN_HAS_PSINFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (cfg->u.rx.err_mode == DMA_RETRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) v |= CHAN_ERR_RETRY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) v |= (cfg->u.rx.desc_type & DESC_TYPE_MASK) << DESC_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (cfg->u.rx.psinfo_at_sop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) v |= CHAN_PSINFO_AT_SOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) v |= (cfg->u.rx.sop_offset & CHAN_SOP_OFF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) << CHAN_SOP_OFF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) v |= cfg->u.rx.dst_q & CHAN_QNUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel_relaxed(v, &chan->reg_rx_flow->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) writel_relaxed(0, &chan->reg_rx_flow->tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) v = cfg->u.rx.fdq[0] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) v |= cfg->u.rx.fdq[1] & CHAN_QNUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) v = cfg->u.rx.fdq[2] << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) v |= cfg->u.rx.fdq[3] & CHAN_QNUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Keep a copy of the cfg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) memcpy(&chan->cfg, cfg, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) spin_unlock(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int chan_teardown(struct knav_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned long end, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!chan->reg_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* indicate teardown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel_relaxed(DMA_TEARDOWN, &chan->reg_chan->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* wait for the dma to shut itself down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) end = jiffies + msecs_to_jiffies(DMA_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) value = readl_relaxed(&chan->reg_chan->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if ((value & DMA_ENABLE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) } while (time_after(end, jiffies));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (readl_relaxed(&chan->reg_chan->control) & DMA_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_err(kdev->dev, "timeout waiting for teardown\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void chan_stop(struct knav_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_lock(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (chan->reg_rx_flow) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* first detach fdqs, starve out the flow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* teardown the dma channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) chan_teardown(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* then disconnect the completion side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (chan->reg_rx_flow) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel_relaxed(0, &chan->reg_rx_flow->control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writel_relaxed(0, &chan->reg_rx_flow->tags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) memset(&chan->cfg, 0, sizeof(struct knav_dma_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spin_unlock(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_dbg(kdev->dev, "channel stopped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void dma_hw_enable_all(struct knav_dma_device *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) for (i = 0; i < dma->max_tx_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) writel_relaxed(0, &dma->reg_tx_chan[i].mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) writel_relaxed(DMA_ENABLE, &dma->reg_tx_chan[i].control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void knav_dma_hw_init(struct knav_dma_device *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) spin_lock(&dma->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) v = dma->loopback ? DMA_LOOPBACK : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel_relaxed(v, &dma->reg_global->emulation_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) v = readl_relaxed(&dma->reg_global->perf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) v |= ((dma->rx_timeout & DMA_RX_TIMEOUT_MASK) << DMA_RX_TIMEOUT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) writel_relaxed(v, &dma->reg_global->perf_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) v = ((dma->tx_priority << DMA_TX_PRIO_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) (dma->rx_priority << DMA_RX_PRIO_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) writel_relaxed(v, &dma->reg_global->priority_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Always enable all Rx channels. Rx paths are managed using flows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) for (i = 0; i < dma->max_rx_chan; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel_relaxed(DMA_ENABLE, &dma->reg_rx_chan[i].control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) for (i = 0; i < dma->logical_queue_managers; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) writel_relaxed(dma->qm_base_address[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) &dma->reg_global->qm_base_address[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) spin_unlock(&dma->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void knav_dma_hw_destroy(struct knav_dma_device *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_lock(&dma->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) v = ~DMA_ENABLE & REG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (i = 0; i < dma->max_rx_chan; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) writel_relaxed(v, &dma->reg_rx_chan[i].control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (i = 0; i < dma->max_tx_chan; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel_relaxed(v, &dma->reg_tx_chan[i].control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spin_unlock(&dma->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void dma_debug_show_channels(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct knav_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) seq_printf(s, "\t%s %d:\t",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ((chan->direction == DMA_MEM_TO_DEV) ? "tx chan" : "rx flow"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) chan_number(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (chan->direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) seq_printf(s, "einfo - %d, pswords - %d, priority - %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) chan->cfg.u.tx.filt_einfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) chan->cfg.u.tx.filt_pswords,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) chan->cfg.u.tx.priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) seq_printf(s, "einfo - %d, psinfo - %d, desc_type - %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) chan->cfg.u.rx.einfo_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) chan->cfg.u.rx.psinfo_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) chan->cfg.u.rx.desc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) seq_printf(s, "\t\t\tdst_q: [%d], thresh: %d fdq: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) chan->cfg.u.rx.dst_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) chan->cfg.u.rx.thresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) for (i = 0; i < KNAV_DMA_FDQ_PER_CHAN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) seq_printf(s, "[%d]", chan->cfg.u.rx.fdq[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) seq_printf(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static void dma_debug_show_devices(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct knav_dma_device *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct knav_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) list_for_each_entry(chan, &dma->chan_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (atomic_read(&chan->ref_count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dma_debug_show_channels(s, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int knav_dma_debug_show(struct seq_file *s, void *v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct knav_dma_device *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) list_for_each_entry(dma, &kdev->list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (atomic_read(&dma->ref_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) seq_printf(s, "%s : max_tx_chan: (%d), max_rx_flows: (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dma->name, dma->max_tx_chan, dma->max_rx_flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dma_debug_show_devices(s, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DEFINE_SHOW_ATTRIBUTE(knav_dma_debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int of_channel_match_helper(struct device_node *np, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) const char **dma_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct device_node *dma_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dma_node = of_parse_phandle(np, "ti,navigator-dmas", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!dma_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *dma_instance = dma_node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) index = of_property_match_string(np, "ti,navigator-dma-names", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_err(kdev->dev, "No 'ti,navigator-dma-names' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (of_parse_phandle_with_fixed_args(np, "ti,navigator-dmas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 1, index, &args)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(kdev->dev, "Missing the phandle args name %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (args.args[0] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(kdev->dev, "Missing args for %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * knav_dma_open_channel() - try to setup an exclusive slave channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @dev: pointer to client device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * @name: slave channel name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @config: dma configuration parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * Returns pointer to appropriate DMA channel on success or error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void *knav_dma_open_channel(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct knav_dma_cfg *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct knav_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct knav_dma_device *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int chan_num = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) const char *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (!kdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pr_err("keystone-navigator-dma driver not registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return (void *)-EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) chan_num = of_channel_match_helper(dev->of_node, name, &instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (chan_num < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_err(kdev->dev, "No DMA instance with name %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return (void *)-EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_dbg(kdev->dev, "initializing %s channel %d from DMA %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) config->direction == DMA_MEM_TO_DEV ? "transmit" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) config->direction == DMA_DEV_TO_MEM ? "receive" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "unknown", chan_num, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (config->direction != DMA_MEM_TO_DEV &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) config->direction != DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_err(kdev->dev, "bad direction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return (void *)-EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Look for correct dma instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) list_for_each_entry(dma, &kdev->list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!strcmp(dma->name, instance)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(kdev->dev, "No DMA instance with name %s\n", instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return (void *)-EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Look for correct dma channel from dma instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) list_for_each_entry(chan, &dma->chan_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (config->direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (chan->channel == chan_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (chan->flow == chan_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_err(kdev->dev, "channel %d is not in DMA %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) chan_num, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return (void *)-EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (atomic_read(&chan->ref_count) >= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!check_config(chan, config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(kdev->dev, "channel %d config miss-match\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) chan_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return (void *)-EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (atomic_inc_return(&chan->dma->ref_count) <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) knav_dma_hw_init(chan->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (atomic_inc_return(&chan->ref_count) <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) chan_start(chan, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_dbg(kdev->dev, "channel %d opened from DMA %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) chan_num, instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) EXPORT_SYMBOL_GPL(knav_dma_open_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * knav_dma_close_channel() - Destroy a dma channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * channel: dma channel handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) void knav_dma_close_channel(void *channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct knav_dma_chan *chan = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!kdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pr_err("keystone-navigator-dma driver not registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (atomic_dec_return(&chan->ref_count) <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) chan_stop(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (atomic_dec_return(&chan->dma->ref_count) <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) knav_dma_hw_destroy(chan->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev_dbg(kdev->dev, "channel %d or flow %d closed from DMA %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) chan->channel, chan->flow, chan->dma->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) EXPORT_SYMBOL_GPL(knav_dma_close_channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static void __iomem *pktdma_get_regs(struct knav_dma_device *dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned index, resource_size_t *_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct device *dev = kdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ret = of_address_to_resource(node, index, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_err(dev, "Can't translate of node(%pOFn) address for index(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) node, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) regs = devm_ioremap_resource(kdev->dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_err(dev, "Failed to map register base for index(%d) node(%pOFn)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) index, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) *_size = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int pktdma_init_rx_chan(struct knav_dma_chan *chan, u32 flow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct knav_dma_device *dma = chan->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) chan->flow = flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) chan->reg_rx_flow = dma->reg_rx_flow + flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) chan->channel = DMA_INVALID_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_dbg(kdev->dev, "rx flow(%d) (%p)\n", chan->flow, chan->reg_rx_flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int pktdma_init_tx_chan(struct knav_dma_chan *chan, u32 channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct knav_dma_device *dma = chan->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) chan->channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) chan->reg_chan = dma->reg_tx_chan + channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) chan->reg_tx_sched = dma->reg_tx_sched + channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) chan->flow = DMA_INVALID_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_dbg(kdev->dev, "tx channel(%d) (%p)\n", chan->channel, chan->reg_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int pktdma_init_chan(struct knav_dma_device *dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned chan_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct device *dev = kdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct knav_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) chan = devm_kzalloc(dev, sizeof(*chan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) INIT_LIST_HEAD(&chan->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) chan->dma = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) chan->direction = DMA_TRANS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) atomic_set(&chan->ref_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) spin_lock_init(&chan->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) chan->direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = pktdma_init_tx_chan(chan, chan_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) } else if (dir == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) chan->direction = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = pktdma_init_rx_chan(chan, chan_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev_err(dev, "channel(%d) direction unknown\n", chan_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) list_add_tail(&chan->list, &dma->chan_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static int dma_init(struct device_node *cloud, struct device_node *dma_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned max_tx_chan, max_rx_chan, max_rx_flow, max_tx_sched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct device_node *node = dma_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct knav_dma_device *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int ret, len, num_chan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dma = devm_kzalloc(kdev->dev, sizeof(*dma), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_err(kdev->dev, "could not allocate driver mem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) INIT_LIST_HEAD(&dma->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) INIT_LIST_HEAD(&dma->chan_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!of_find_property(cloud, "ti,navigator-cloud-address", &len)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_err(kdev->dev, "unspecified navigator cloud addresses\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dma->logical_queue_managers = len / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (dma->logical_queue_managers > DMA_MAX_QMS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_warn(kdev->dev, "too many queue mgrs(>%d) rest ignored\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dma->logical_queue_managers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dma->logical_queue_managers = DMA_MAX_QMS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = of_property_read_u32_array(cloud, "ti,navigator-cloud-address",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dma->qm_base_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dma->logical_queue_managers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dev_err(kdev->dev, "invalid navigator cloud addresses\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dma->reg_global = pktdma_get_regs(dma, node, 0, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!dma->reg_global)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (size < sizeof(struct reg_global)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_err(kdev->dev, "bad size %pa for global regs\n", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dma->reg_tx_chan = pktdma_get_regs(dma, node, 1, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!dma->reg_tx_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) max_tx_chan = size / sizeof(struct reg_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dma->reg_rx_chan = pktdma_get_regs(dma, node, 2, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!dma->reg_rx_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) max_rx_chan = size / sizeof(struct reg_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dma->reg_tx_sched = pktdma_get_regs(dma, node, 3, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (!dma->reg_tx_sched)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) max_tx_sched = size / sizeof(struct reg_tx_sched);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dma->reg_rx_flow = pktdma_get_regs(dma, node, 4, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!dma->reg_rx_flow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) max_rx_flow = size / sizeof(struct reg_rx_flow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dma->rx_priority = DMA_PRIO_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dma->tx_priority = DMA_PRIO_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dma->enable_all = (of_get_property(node, "ti,enable-all", NULL) != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dma->loopback = (of_get_property(node, "ti,loop-back", NULL) != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = of_property_read_u32(node, "ti,rx-retry-timeout", &timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_dbg(kdev->dev, "unspecified rx timeout using value %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) DMA_RX_TIMEOUT_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) timeout = DMA_RX_TIMEOUT_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dma->rx_timeout = timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dma->max_rx_chan = max_rx_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dma->max_rx_flow = max_rx_flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dma->max_tx_chan = min(max_tx_chan, max_tx_sched);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) atomic_set(&dma->ref_count, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) strcpy(dma->name, node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) spin_lock_init(&dma->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) for (i = 0; i < dma->max_tx_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (pktdma_init_chan(dma, DMA_MEM_TO_DEV, i) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) num_chan++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) for (i = 0; i < dma->max_rx_flow; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (pktdma_init_chan(dma, DMA_DEV_TO_MEM, i) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) num_chan++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) list_add_tail(&dma->list, &kdev->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * For DSP software usecases or userpace transport software, setup all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * the DMA hardware resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (dma->enable_all) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) atomic_inc(&dma->ref_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) knav_dma_hw_init(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dma_hw_enable_all(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_info(kdev->dev, "DMA %s registered %d logical channels, flows %d, tx chans: %d, rx chans: %d%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dma->name, num_chan, dma->max_rx_flow,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dma->max_tx_chan, dma->max_rx_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dma->loopback ? ", loopback" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static int knav_dma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_err(&pdev->dev, "could not find device info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) kdev = devm_kzalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) sizeof(struct knav_dma_pool_device), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!kdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_err(dev, "could not allocate driver mem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) kdev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) INIT_LIST_HEAD(&kdev->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pm_runtime_enable(kdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = pm_runtime_get_sync(kdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) pm_runtime_put_noidle(kdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_err(kdev->dev, "unable to enable pktdma, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* Initialise all packet dmas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) for_each_child_of_node(node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = dma_init(node, child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_err(&pdev->dev, "init failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (list_empty(&kdev->list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_err(dev, "no valid dma instance\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto err_put_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) debugfs_create_file("knav_dma", S_IFREG | S_IRUGO, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) &knav_dma_debug_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) device_ready = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) err_put_sync:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) pm_runtime_put_sync(kdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) pm_runtime_disable(kdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static int knav_dma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct knav_dma_device *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) list_for_each_entry(dma, &kdev->list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (atomic_dec_return(&dma->ref_count) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) knav_dma_hw_destroy(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static struct of_device_id of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { .compatible = "ti,keystone-navigator-dma", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) MODULE_DEVICE_TABLE(of, of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static struct platform_driver knav_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .probe = knav_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .remove = knav_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .name = "keystone-navigator-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .of_match_table = of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) module_platform_driver(knav_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) MODULE_DESCRIPTION("TI Keystone Navigator Packet DMA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) MODULE_AUTHOR("Sandeep Nair <sandeep_n@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) MODULE_AUTHOR("Santosh Shilimkar <santosh.shilimkar@ti.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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