^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Voltage regulators coupler for NVIDIA Tegra30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 GRATE-DRIVER project
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Voltage constraints borrowed from downstream kernel sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010-2011 NVIDIA Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/coupler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct tegra_regulator_coupler {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct regulator_coupler coupler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct regulator_dev *core_rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regulator_dev *cpu_rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int core_min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline struct tegra_regulator_coupler *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) to_tegra_coupler(struct regulator_coupler *coupler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return container_of(coupler, struct tegra_regulator_coupler, coupler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int tegra30_core_limit(struct tegra_regulator_coupler *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct regulator_dev *core_rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int core_min_uV = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int core_max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int core_cur_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (tegra->core_min_uV > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return tegra->core_min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) core_cur_uV = regulator_get_voltage_rdev(core_rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (core_cur_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return core_cur_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) core_max_uV = max(core_cur_uV, 1200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) err = regulator_check_voltage(core_rdev, &core_min_uV, &core_max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Limit minimum CORE voltage to a value left from bootloader or,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * if it's unreasonably low value, to the most common 1.2v or to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * whatever maximum value defined via board's device-tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) tegra->core_min_uV = core_max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return tegra->core_min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int tegra30_core_cpu_limit(int cpu_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (cpu_uV < 800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return 950000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (cpu_uV < 900000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (cpu_uV < 1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 1100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (cpu_uV < 1100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 1200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (cpu_uV < 1250000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) switch (tegra_sku_info.cpu_speedo_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case 0 ... 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case 7 ... 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 1200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 1300000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int tegra30_voltage_update(struct tegra_regulator_coupler *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regulator_dev *cpu_rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct regulator_dev *core_rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int core_min_uV, core_max_uV = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int cpu_min_uV, cpu_max_uV = INT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int cpu_min_uV_consumers = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int core_min_limited_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int core_target_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int cpu_target_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int core_max_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int cpu_max_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int max_spread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int core_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int cpu_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * CPU voltage should not got lower than 300mV from the CORE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * CPU voltage should stay below the CORE by 100mV+, depending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * by the CORE voltage. This applies to all Tegra30 SoC's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) max_spread = cpu_rdev->constraints->max_spread[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cpu_max_step = cpu_rdev->constraints->max_uV_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) core_max_step = core_rdev->constraints->max_uV_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!max_spread) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_err_once("cpu-core max-spread is undefined in device-tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) max_spread = 300000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!cpu_max_step) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pr_err_once("cpu max-step is undefined in device-tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) cpu_max_step = 150000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!core_max_step) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_err_once("core max-step is undefined in device-tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) core_max_step = 150000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * The CORE voltage scaling is currently not hooked up in drivers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * hence we will limit the minimum CORE voltage to a reasonable value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * This should be good enough for the time being.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) core_min_uV = tegra30_core_limit(tegra, core_rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (core_min_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return core_min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) err = regulator_check_consumers(core_rdev, &core_min_uV, &core_max_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PM_SUSPEND_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) core_uV = regulator_get_voltage_rdev(core_rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (core_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return core_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cpu_min_uV = core_min_uV - max_spread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) err = regulator_check_consumers(cpu_rdev, &cpu_min_uV, &cpu_max_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PM_SUSPEND_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) err = regulator_check_consumers(cpu_rdev, &cpu_min_uV_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &cpu_max_uV, PM_SUSPEND_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) err = regulator_check_voltage(cpu_rdev, &cpu_min_uV, &cpu_max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) cpu_uV = regulator_get_voltage_rdev(cpu_rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (cpu_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return cpu_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * CPU's regulator may not have any consumers, hence the voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * must not be changed in that case because CPU simply won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * survive the voltage drop if it's running on a higher frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!cpu_min_uV_consumers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) cpu_min_uV = max(cpu_uV, cpu_min_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Bootloader shall set up voltages correctly, but if it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * happens that there is a violation, then try to fix it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * at first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) core_min_limited_uV = tegra30_core_cpu_limit(cpu_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (core_min_limited_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return core_min_limited_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) core_min_uV = max(core_min_uV, tegra30_core_cpu_limit(cpu_min_uV));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) err = regulator_check_voltage(core_rdev, &core_min_uV, &core_max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (core_min_limited_uV > core_uV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pr_err("core voltage constraint violated: %d %d %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) core_uV, core_min_limited_uV, cpu_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto update_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) while (cpu_uV != cpu_min_uV || core_uV != core_min_uV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (cpu_uV < cpu_min_uV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) cpu_target_uV = min(cpu_uV + cpu_max_step, cpu_min_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) cpu_target_uV = max(cpu_uV - cpu_max_step, cpu_min_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cpu_target_uV = max(core_uV - max_spread, cpu_target_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (cpu_uV == cpu_target_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto update_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) err = regulator_set_voltage_rdev(cpu_rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) cpu_target_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) cpu_max_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PM_SUSPEND_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) cpu_uV = cpu_target_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) update_core:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) core_min_limited_uV = tegra30_core_cpu_limit(cpu_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (core_min_limited_uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return core_min_limited_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) core_target_uV = max(core_min_limited_uV, core_min_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (core_uV < core_target_uV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) core_target_uV = min(core_target_uV, core_uV + core_max_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) core_target_uV = min(core_target_uV, cpu_uV + max_spread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) core_target_uV = max(core_target_uV, core_uV - core_max_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (core_uV == core_target_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) err = regulator_set_voltage_rdev(core_rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) core_target_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) core_max_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PM_SUSPEND_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) core_uV = core_target_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int tegra30_regulator_balance_voltage(struct regulator_coupler *coupler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct regulator_dev *core_rdev = tegra->core_rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct regulator_dev *cpu_rdev = tegra->cpu_rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if ((core_rdev != rdev && cpu_rdev != rdev) || state != PM_SUSPEND_ON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_err("regulators are not coupled properly\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return tegra30_voltage_update(tegra, cpu_rdev, core_rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int tegra30_regulator_attach(struct regulator_coupler *coupler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device_node *np = rdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (of_property_read_bool(np, "nvidia,tegra-core-regulator") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) !tegra->core_rdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tegra->core_rdev = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (of_property_read_bool(np, "nvidia,tegra-cpu-regulator") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) !tegra->cpu_rdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) tegra->cpu_rdev = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int tegra30_regulator_detach(struct regulator_coupler *coupler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct tegra_regulator_coupler *tegra = to_tegra_coupler(coupler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (tegra->core_rdev == rdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) tegra->core_rdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (tegra->cpu_rdev == rdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tegra->cpu_rdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static struct tegra_regulator_coupler tegra30_coupler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .coupler = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .attach_regulator = tegra30_regulator_attach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .detach_regulator = tegra30_regulator_detach,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .balance_voltage = tegra30_regulator_balance_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int __init tegra_regulator_coupler_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!of_machine_is_compatible("nvidia,tegra30"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return regulator_coupler_register(&tegra30_coupler.coupler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) arch_initcall(tegra_regulator_coupler_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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