^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "fuse.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SOC_PROCESS_CORNERS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CPU_PROCESS_CORNERS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FUSE_SPEEDO_CALIB_0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FUSE_PACKAGE_INFO 0XFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define FUSE_TEST_PROG_VER 0X28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define G_SPEEDO_BIT_MINUS1 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define G_SPEEDO_BIT_MINUS1_R 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define G_SPEEDO_BIT_MINUS2 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define G_SPEEDO_BIT_MINUS2_R 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LP_SPEEDO_BIT_MINUS1 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP_SPEEDO_BIT_MINUS1_R 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP_SPEEDO_BIT_MINUS2 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP_SPEEDO_BIT_MINUS2_R 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) THRESHOLD_INDEX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) THRESHOLD_INDEX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) THRESHOLD_INDEX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) THRESHOLD_INDEX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) THRESHOLD_INDEX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) THRESHOLD_INDEX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) THRESHOLD_INDEX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) THRESHOLD_INDEX_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) THRESHOLD_INDEX_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) THRESHOLD_INDEX_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) THRESHOLD_INDEX_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) THRESHOLD_INDEX_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) THRESHOLD_INDEX_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const u32 __initconst soc_process_speedos[][SOC_PROCESS_CORNERS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {170},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {195},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {168},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {192},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {170},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {195},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const u32 __initconst cpu_process_speedos[][CPU_PROCESS_CORNERS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {306, 338, 360, 376, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {295, 336, 358, 375, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {325, 325, 358, 375, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {325, 325, 358, 375, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {292, 324, 348, 364, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {324, 324, 348, 364, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {324, 324, 348, 364, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {295, 336, 358, 375, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {358, 358, 358, 358, 397, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {364, 364, 364, 364, 397, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {295, 336, 358, 375, 391, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {295, 336, 358, 375, 391, UINT_MAX},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int threshold_index __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void __init fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ate_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int bit_minus1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int bit_minus2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg = tegra_fuse_read_early(FUSE_SPEEDO_CALIB_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *speedo_lp = (reg & 0xFFFF) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *speedo_g = ((reg >> 16) & 0xFFFF) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ate_ver = tegra_fuse_read_early(FUSE_TEST_PROG_VER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pr_debug("Tegra ATE prog ver %d.%d\n", ate_ver/10, ate_ver%10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (ate_ver >= 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) bit_minus1 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bit_minus1 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS1_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bit_minus2 = tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bit_minus2 |= tegra_fuse_read_spare(LP_SPEEDO_BIT_MINUS2_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *speedo_lp |= (bit_minus1 << 1) | bit_minus2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bit_minus1 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bit_minus1 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS1_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bit_minus2 = tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bit_minus2 |= tegra_fuse_read_spare(G_SPEEDO_BIT_MINUS2_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *speedo_g |= (bit_minus1 << 1) | bit_minus2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *speedo_lp |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *speedo_g |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int package_id = tegra_fuse_read_early(FUSE_PACKAGE_INFO) & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (sku_info->revision) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case TEGRA_REVISION_A01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) sku_info->cpu_speedo_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) sku_info->soc_speedo_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) threshold_index = THRESHOLD_INDEX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case TEGRA_REVISION_A02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case TEGRA_REVISION_A03:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) switch (sku_info->sku_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case 0x87:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case 0x82:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) sku_info->cpu_speedo_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) sku_info->soc_speedo_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) threshold_index = THRESHOLD_INDEX_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case 0x81:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) switch (package_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) sku_info->cpu_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) sku_info->soc_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) threshold_index = THRESHOLD_INDEX_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) sku_info->cpu_speedo_id = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) sku_info->soc_speedo_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) threshold_index = THRESHOLD_INDEX_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pr_err("Tegra Unknown pkg %d\n", package_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case 0x80:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) switch (package_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sku_info->cpu_speedo_id = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sku_info->soc_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) threshold_index = THRESHOLD_INDEX_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) sku_info->cpu_speedo_id = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sku_info->soc_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) threshold_index = THRESHOLD_INDEX_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pr_err("Tegra Unknown pkg %d\n", package_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) case 0x83:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (package_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) sku_info->cpu_speedo_id = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) sku_info->soc_speedo_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) threshold_index = THRESHOLD_INDEX_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sku_info->cpu_speedo_id = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sku_info->soc_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) threshold_index = THRESHOLD_INDEX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pr_err("Tegra Unknown pkg %d\n", package_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case 0x8F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) sku_info->cpu_speedo_id = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) sku_info->soc_speedo_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) threshold_index = THRESHOLD_INDEX_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case 0x08:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) sku_info->cpu_speedo_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sku_info->soc_speedo_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) threshold_index = THRESHOLD_INDEX_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case 0x02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) sku_info->cpu_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) sku_info->soc_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) threshold_index = THRESHOLD_INDEX_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case 0x04:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sku_info->cpu_speedo_id = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) sku_info->soc_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) threshold_index = THRESHOLD_INDEX_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) switch (package_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) sku_info->cpu_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) sku_info->soc_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) threshold_index = THRESHOLD_INDEX_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) sku_info->cpu_speedo_id = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) sku_info->soc_speedo_id = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) threshold_index = THRESHOLD_INDEX_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_err("Tegra Unknown pkg %d\n", package_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pr_warn("Tegra Unknown SKU %d\n", sku_info->sku_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) sku_info->cpu_speedo_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) sku_info->soc_speedo_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) threshold_index = THRESHOLD_INDEX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pr_warn("Tegra Unknown chip rev %d\n", sku_info->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) sku_info->cpu_speedo_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sku_info->soc_speedo_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) threshold_index = THRESHOLD_INDEX_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void __init tegra30_init_speedo_data(struct tegra_sku_info *sku_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 cpu_speedo_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 soc_speedo_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) THRESHOLD_INDEX_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) THRESHOLD_INDEX_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) rev_sku_to_speedo_ids(sku_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) fuse_speedo_calib(&cpu_speedo_val, &soc_speedo_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pr_debug("Tegra CPU speedo value %u\n", cpu_speedo_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_debug("Tegra Core speedo value %u\n", soc_speedo_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < CPU_PROCESS_CORNERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) sku_info->cpu_process_id = i - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (sku_info->cpu_process_id == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pr_warn("Tegra CPU speedo value %3d out of range",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) cpu_speedo_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) sku_info->cpu_process_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) sku_info->cpu_speedo_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) for (i = 0; i < SOC_PROCESS_CORNERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (soc_speedo_val < soc_process_speedos[threshold_index][i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sku_info->soc_process_id = i - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (sku_info->soc_process_id == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pr_warn("Tegra SoC speedo value %3d out of range",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) soc_speedo_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) sku_info->soc_process_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sku_info->soc_speedo_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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