^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Colin Cross <ccross@android.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DRIVERS_MISC_TEGRA_FUSE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DRIVERS_MISC_TEGRA_FUSE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct nvmem_cell_lookup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct nvmem_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct tegra_fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct tegra_fuse_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int spare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct tegra_fuse_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void (*init)(struct tegra_fuse *fuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void (*speedo_init)(struct tegra_sku_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int (*probe)(struct tegra_fuse *fuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const struct tegra_fuse_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const struct nvmem_cell_lookup *lookups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int num_lookups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const struct attribute_group *soc_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct tegra_fuse {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) phys_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 (*read_early)(struct tegra_fuse *fuse, unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 (*read)(struct tegra_fuse *fuse, unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const struct tegra_fuse_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* APBDMA on Tegra20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct completion wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } apbdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct nvmem_device *nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct nvmem_cell_lookup *lookups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void tegra_init_revision(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void tegra_init_apbmisc(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 __init tegra_fuse_read_spare(unsigned int spare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 __init tegra_fuse_read_early(unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 tegra_get_major_rev(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 tegra_get_minor_rev(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern const struct attribute_group tegra_soc_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifdef CONFIG_ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) void tegra20_init_speedo_data(struct tegra_sku_info *sku_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef CONFIG_ARCH_TEGRA_3x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void tegra30_init_speedo_data(struct tegra_sku_info *sku_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_ARCH_TEGRA_114_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void tegra114_init_speedo_data(struct tegra_sku_info *sku_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) void tegra124_init_speedo_data(struct tegra_sku_info *sku_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef CONFIG_ARCH_TEGRA_210_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void tegra210_init_speedo_data(struct tegra_sku_info *sku_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CONFIG_ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) extern const struct tegra_fuse_soc tegra20_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_ARCH_TEGRA_3x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) extern const struct tegra_fuse_soc tegra30_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef CONFIG_ARCH_TEGRA_114_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) extern const struct tegra_fuse_soc tegra114_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) extern const struct tegra_fuse_soc tegra124_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #ifdef CONFIG_ARCH_TEGRA_210_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) extern const struct tegra_fuse_soc tegra210_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef CONFIG_ARCH_TEGRA_186_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern const struct tegra_fuse_soc tegra186_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) extern const struct attribute_group tegra194_soc_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #ifdef CONFIG_ARCH_TEGRA_194_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) extern const struct tegra_fuse_soc tegra194_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef CONFIG_ARCH_TEGRA_234_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern const struct tegra_fuse_soc tegra234_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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