^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "fuse.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FUSE_BEGIN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Tegra30 and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FUSE_VENDOR_CODE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FUSE_FAB_CODE 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FUSE_LOT_CODE_0 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FUSE_LOT_CODE_1 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FUSE_WAFER_ID 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FUSE_X_COORDINATE 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FUSE_Y_COORDINATE 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FUSE_HAS_REVISION_INFO BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) defined(CONFIG_ARCH_TEGRA_114_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) defined(CONFIG_ARCH_TEGRA_124_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) defined(CONFIG_ARCH_TEGRA_132_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) defined(CONFIG_ARCH_TEGRA_210_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) defined(CONFIG_ARCH_TEGRA_186_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) defined(CONFIG_ARCH_TEGRA_194_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) defined(CONFIG_ARCH_TEGRA_234_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (WARN_ON(!fuse->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) err = clk_prepare_enable(fuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) value = readl_relaxed(fuse->base + FUSE_BEGIN + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clk_disable_unprepare(fuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void __init tegra30_fuse_add_randomness(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 randomness[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) randomness[0] = tegra_sku_info.sku_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) randomness[1] = tegra_read_straps();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) randomness[2] = tegra_read_chipid();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) randomness[3] = tegra_sku_info.cpu_process_id << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) randomness[3] |= tegra_sku_info.soc_process_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) randomness[4] |= tegra_sku_info.soc_speedo_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) add_device_randomness(randomness, sizeof(randomness));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) fuse->read_early = tegra30_fuse_read_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) fuse->read = tegra30_fuse_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tegra_init_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (fuse->soc->speedo_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) fuse->soc->speedo_init(&tegra_sku_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tegra30_fuse_add_randomness();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #ifdef CONFIG_ARCH_TEGRA_3x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct tegra_fuse_info tegra30_fuse_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .read = tegra30_fuse_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .size = 0x2a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .spare = 0x144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const struct tegra_fuse_soc tegra30_fuse_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .init = tegra30_fuse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .speedo_init = tegra30_init_speedo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .info = &tegra30_fuse_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .soc_attr_group = &tegra_soc_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #ifdef CONFIG_ARCH_TEGRA_114_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct tegra_fuse_info tegra114_fuse_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .read = tegra30_fuse_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .size = 0x2a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .spare = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct tegra_fuse_soc tegra114_fuse_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .init = tegra30_fuse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .speedo_init = tegra114_init_speedo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .info = &tegra114_fuse_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .soc_attr_group = &tegra_soc_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct nvmem_cell_lookup tegra124_fuse_lookups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .cell_name = "xusb-pad-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .dev_id = "7009f000.padctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .con_id = "calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .cell_name = "sata-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .dev_id = "70020000.sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .con_id = "calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .cell_name = "tsensor-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .con_id = "common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .cell_name = "tsensor-realignment",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .con_id = "realignment",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .cell_name = "tsensor-cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .con_id = "cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .cell_name = "tsensor-cpu1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .con_id = "cpu1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .cell_name = "tsensor-cpu2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .con_id = "cpu2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .cell_name = "tsensor-cpu3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .con_id = "cpu3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .cell_name = "tsensor-mem0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .con_id = "mem0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .cell_name = "tsensor-mem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .con_id = "mem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .cell_name = "tsensor-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .con_id = "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .cell_name = "tsensor-pllx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .con_id = "pllx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct tegra_fuse_info tegra124_fuse_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .read = tegra30_fuse_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .size = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .spare = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const struct tegra_fuse_soc tegra124_fuse_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .init = tegra30_fuse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .speedo_init = tegra124_init_speedo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .info = &tegra124_fuse_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .lookups = tegra124_fuse_lookups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .num_lookups = ARRAY_SIZE(tegra124_fuse_lookups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .soc_attr_group = &tegra_soc_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #if defined(CONFIG_ARCH_TEGRA_210_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct nvmem_cell_lookup tegra210_fuse_lookups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .cell_name = "tsensor-cpu1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .con_id = "cpu1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .cell_name = "tsensor-cpu2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .con_id = "cpu2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .cell_name = "tsensor-cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .con_id = "cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .cell_name = "xusb-pad-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .dev_id = "7009f000.padctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .con_id = "calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .cell_name = "tsensor-cpu3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .con_id = "cpu3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .cell_name = "sata-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .dev_id = "70020000.sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .con_id = "calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .cell_name = "tsensor-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .con_id = "gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .cell_name = "tsensor-mem0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .con_id = "mem0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .cell_name = "tsensor-mem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .con_id = "mem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .cell_name = "tsensor-pllx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .con_id = "pllx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .cell_name = "tsensor-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .dev_id = "700e2000.thermal-sensor",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .con_id = "common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .cell_name = "gpu-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .dev_id = "57000000.gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .con_id = "calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .cell_name = "xusb-pad-calibration-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .dev_id = "7009f000.padctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .con_id = "calibration-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct tegra_fuse_info tegra210_fuse_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .read = tegra30_fuse_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .size = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .spare = 0x280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const struct tegra_fuse_soc tegra210_fuse_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .init = tegra30_fuse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .speedo_init = tegra210_init_speedo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .info = &tegra210_fuse_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .lookups = tegra210_fuse_lookups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .num_lookups = ARRAY_SIZE(tegra210_fuse_lookups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .soc_attr_group = &tegra_soc_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #if defined(CONFIG_ARCH_TEGRA_186_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct nvmem_cell_lookup tegra186_fuse_lookups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .cell_name = "xusb-pad-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .dev_id = "3520000.padctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .con_id = "calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .cell_name = "xusb-pad-calibration-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .dev_id = "3520000.padctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .con_id = "calibration-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct tegra_fuse_info tegra186_fuse_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .read = tegra30_fuse_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .size = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .spare = 0x280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) const struct tegra_fuse_soc tegra186_fuse_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .init = tegra30_fuse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .info = &tegra186_fuse_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .lookups = tegra186_fuse_lookups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .num_lookups = ARRAY_SIZE(tegra186_fuse_lookups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .soc_attr_group = &tegra_soc_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #if defined(CONFIG_ARCH_TEGRA_194_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .cell_name = "xusb-pad-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .dev_id = "3520000.padctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .con_id = "calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .cell_name = "xusb-pad-calibration-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .dev_id = "3520000.padctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .con_id = "calibration-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const struct tegra_fuse_info tegra194_fuse_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .read = tegra30_fuse_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .size = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .spare = 0x280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct tegra_fuse_soc tegra194_fuse_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .init = tegra30_fuse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .info = &tegra194_fuse_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .lookups = tegra194_fuse_lookups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .num_lookups = ARRAY_SIZE(tegra194_fuse_lookups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .soc_attr_group = &tegra194_soc_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #if defined(CONFIG_ARCH_TEGRA_234_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct nvmem_cell_lookup tegra234_fuse_lookups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .cell_name = "xusb-pad-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .dev_id = "3520000.padctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .con_id = "calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .nvmem_name = "fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .cell_name = "xusb-pad-calibration-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .dev_id = "3520000.padctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .con_id = "calibration-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct tegra_fuse_info tegra234_fuse_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .read = tegra30_fuse_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .size = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .spare = 0x280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) const struct tegra_fuse_soc tegra234_fuse_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .init = tegra30_fuse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .info = &tegra234_fuse_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .lookups = tegra234_fuse_lookups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .num_lookups = ARRAY_SIZE(tegra234_fuse_lookups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .soc_attr_group = &tegra194_soc_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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