^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on drivers/misc/eeprom/sunxi_sid.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kobject.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "fuse.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FUSE_BEGIN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FUSE_UID_LOW 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FUSE_UID_HIGH 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static u32 tegra20_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void apb_dma_complete(void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct tegra_fuse *fuse = args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) complete(&fuse->apbdma.wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static u32 tegra20_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned long flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct dma_async_tx_descriptor *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long time_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mutex_lock(&fuse->apbdma.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) fuse->apbdma.config.src_addr = fuse->phys + FUSE_BEGIN + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) err = dmaengine_slave_config(fuse->apbdma.chan, &fuse->apbdma.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dma_desc = dmaengine_prep_slave_single(fuse->apbdma.chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) fuse->apbdma.phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) sizeof(u32), DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!dma_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dma_desc->callback = apb_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dma_desc->callback_param = fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reinit_completion(&fuse->apbdma.wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clk_prepare_enable(fuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) dmaengine_submit(dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dma_async_issue_pending(fuse->apbdma.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) time_left = wait_for_completion_timeout(&fuse->apbdma.wait,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) msecs_to_jiffies(50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (WARN(time_left == 0, "apb read dma timed out"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dmaengine_terminate_all(fuse->apbdma.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) value = *fuse->apbdma.virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk_disable_unprepare(fuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mutex_unlock(&fuse->apbdma.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static bool dma_filter(struct dma_chan *chan, void *filter_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct device_node *np = chan->device->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return of_device_is_compatible(np, "nvidia,tegra20-apbdma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int tegra20_fuse_probe(struct tegra_fuse *fuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) fuse->apbdma.chan = dma_request_channel(mask, dma_filter, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!fuse->apbdma.chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) fuse->apbdma.virt = dma_alloc_coherent(fuse->dev, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) &fuse->apbdma.phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!fuse->apbdma.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dma_release_channel(fuse->apbdma.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) fuse->apbdma.config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) fuse->apbdma.config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) fuse->apbdma.config.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) fuse->apbdma.config.dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) fuse->apbdma.config.direction = DMA_DEV_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) fuse->apbdma.config.device_fc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) init_completion(&fuse->apbdma.wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mutex_init(&fuse->apbdma.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) fuse->read = tegra20_fuse_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct tegra_fuse_info tegra20_fuse_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .read = tegra20_fuse_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .size = 0x1f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .spare = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Early boot code. This code is called before the devices are created */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void __init tegra20_fuse_add_randomness(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 randomness[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) randomness[0] = tegra_sku_info.sku_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) randomness[1] = tegra_read_straps();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) randomness[2] = tegra_read_chipid();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) randomness[3] = tegra_sku_info.cpu_process_id << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) randomness[3] |= tegra_sku_info.soc_process_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) randomness[4] |= tegra_sku_info.soc_speedo_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) randomness[5] = tegra_fuse_read_early(FUSE_UID_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) randomness[6] = tegra_fuse_read_early(FUSE_UID_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) add_device_randomness(randomness, sizeof(randomness));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void __init tegra20_fuse_init(struct tegra_fuse *fuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) fuse->read_early = tegra20_fuse_read_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) tegra_init_revision();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) fuse->soc->speedo_init(&tegra_sku_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) tegra20_fuse_add_randomness();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const struct tegra_fuse_soc tegra20_fuse_soc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .init = tegra20_fuse_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .speedo_init = tegra20_init_speedo_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .probe = tegra20_fuse_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .info = &tegra20_fuse_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .soc_attr_group = &tegra_soc_attr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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