^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kobject.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/nvmem-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <soc/tegra/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "fuse.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct tegra_sku_info tegra_sku_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) EXPORT_SYMBOL(tegra_sku_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [TEGRA_REVISION_UNKNOWN] = "unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [TEGRA_REVISION_A01] = "A01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [TEGRA_REVISION_A02] = "A02",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [TEGRA_REVISION_A03] = "A03",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) [TEGRA_REVISION_A03p] = "A03 prime",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [TEGRA_REVISION_A04] = "A04",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct of_device_id car_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { .compatible = "nvidia,tegra20-car", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { .compatible = "nvidia,tegra30-car", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { .compatible = "nvidia,tegra114-car", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { .compatible = "nvidia,tegra124-car", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { .compatible = "nvidia,tegra132-car", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { .compatible = "nvidia,tegra210-car", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct tegra_fuse *fuse = &(struct tegra_fuse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .base = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .soc = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct of_device_id tegra_fuse_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_ARCH_TEGRA_234_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifdef CONFIG_ARCH_TEGRA_194_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #ifdef CONFIG_ARCH_TEGRA_186_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_ARCH_TEGRA_210_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #ifdef CONFIG_ARCH_TEGRA_132_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef CONFIG_ARCH_TEGRA_124_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_ARCH_TEGRA_114_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #ifdef CONFIG_ARCH_TEGRA_3x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #ifdef CONFIG_ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) size_t bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int count = bytes / 4, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct tegra_fuse *fuse = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 *buffer = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) buffer[i] = fuse->read(fuse, offset + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct nvmem_cell_info tegra_fuse_cells[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .name = "tsensor-cpu1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .offset = 0x084,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "tsensor-cpu2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .offset = 0x088,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .name = "tsensor-cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .offset = 0x098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "xusb-pad-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .offset = 0x0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .name = "tsensor-cpu3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .offset = 0x12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .name = "sata-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .offset = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .bytes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .nbits = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "tsensor-gpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .offset = 0x154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .name = "tsensor-mem0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .offset = 0x158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "tsensor-mem1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .offset = 0x15c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = "tsensor-pllx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .offset = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "tsensor-common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .offset = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .name = "tsensor-realignment",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .offset = 0x1fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "gpu-calibration",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .offset = 0x204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "xusb-pad-calibration-ext",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .offset = 0x250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .bytes = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .bit_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .nbits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int tegra_fuse_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __iomem *base = fuse->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct nvmem_config nvmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* take over the memory region from the early initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) fuse->phys = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) fuse->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (IS_ERR(fuse->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) err = PTR_ERR(fuse->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) fuse->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) fuse->clk = devm_clk_get(&pdev->dev, "fuse");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (IS_ERR(fuse->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (PTR_ERR(fuse->clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_err(&pdev->dev, "failed to get FUSE clock: %ld",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PTR_ERR(fuse->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) fuse->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return PTR_ERR(fuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) platform_set_drvdata(pdev, fuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) fuse->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (fuse->soc->probe) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) err = fuse->soc->probe(fuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) memset(&nvmem, 0, sizeof(nvmem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) nvmem.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) nvmem.name = "fuse";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) nvmem.id = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) nvmem.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) nvmem.cells = tegra_fuse_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) nvmem.ncells = ARRAY_SIZE(tegra_fuse_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) nvmem.type = NVMEM_TYPE_OTP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) nvmem.read_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) nvmem.root_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) nvmem.reg_read = tegra_fuse_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) nvmem.size = fuse->soc->info->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) nvmem.word_size = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) nvmem.stride = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) nvmem.priv = fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (IS_ERR(fuse->nvmem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err = PTR_ERR(fuse->nvmem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) goto restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* release the early I/O memory mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) restore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) fuse->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static struct platform_driver tegra_fuse_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "tegra-fuse",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .of_match_table = tegra_fuse_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .probe = tegra_fuse_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) builtin_platform_driver(tegra_fuse_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 __init tegra_fuse_read_spare(unsigned int spare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int offset = fuse->soc->info->spare + spare * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return fuse->read_early(fuse, offset) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 __init tegra_fuse_read_early(unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return fuse->read_early(fuse, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int tegra_fuse_readl(unsigned long offset, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!fuse->read || !fuse->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (IS_ERR(fuse->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return PTR_ERR(fuse->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *value = fuse->read(fuse, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) EXPORT_SYMBOL(tegra_fuse_readl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void tegra_enable_fuse_clk(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) reg = readl_relaxed(base + 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) reg |= 1 << 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel(reg, base + 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Enable FUSE clock. This needs to be hardcoded because the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * subsystem is not active during early boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) reg = readl(base + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) reg |= 1 << 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(reg, base + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static ssize_t major_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return sprintf(buf, "%d\n", tegra_get_major_rev());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static DEVICE_ATTR_RO(major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static ssize_t minor_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return sprintf(buf, "%d\n", tegra_get_minor_rev());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static DEVICE_ATTR_RO(minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct attribute *tegra_soc_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) &dev_attr_major.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) &dev_attr_minor.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) const struct attribute_group tegra_soc_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .attrs = tegra_soc_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Displays the value in the 'pre_si_platform' field of the HIDREV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * register for Tegra194 devices. A value of 0 indicates that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * platform type is silicon and all other non-zero values indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * the type of simulation platform is being used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return sprintf(buf, "%d\n", tegra_get_platform());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static DEVICE_ATTR_RO(platform);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct attribute *tegra194_soc_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &dev_attr_major.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) &dev_attr_minor.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) &dev_attr_platform.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) const struct attribute_group tegra194_soc_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .attrs = tegra194_soc_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct device * __init tegra_soc_device_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct soc_device_attribute *attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct soc_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) attr = kzalloc(sizeof(*attr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) attr->family = kasprintf(GFP_KERNEL, "Tegra");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) attr->revision = kasprintf(GFP_KERNEL, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) tegra_revision_name[tegra_sku_info.revision]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) attr->custom_attr_group = fuse->soc->soc_attr_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev = soc_device_register(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (IS_ERR(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) kfree(attr->soc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) kfree(attr->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) kfree(attr->family);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) kfree(attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return ERR_CAST(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return soc_device_to_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int __init tegra_init_fuse(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct resource regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) tegra_init_apbmisc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Fall back to legacy initialization for 32-bit ARM only. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * 64-bit ARM device tree files for Tegra are required to have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * a FUSE node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * This is for backwards-compatibility with old device trees
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * that didn't contain a FUSE node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u8 chip = tegra_get_chip_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) regs.start = 0x7000f800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) regs.end = 0x7000fbff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) regs.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) switch (chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #ifdef CONFIG_ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case TEGRA20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) fuse->soc = &tegra20_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #ifdef CONFIG_ARCH_TEGRA_3x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case TEGRA30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) fuse->soc = &tegra30_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #ifdef CONFIG_ARCH_TEGRA_114_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case TEGRA114:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) fuse->soc = &tegra114_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #ifdef CONFIG_ARCH_TEGRA_124_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case TEGRA124:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) fuse->soc = &tegra124_fuse_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pr_warn("Unsupported SoC: %02x\n", chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * At this point we're not running on Tegra, so play
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * nice with multi-platform kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Extract information from the device tree if we've found a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * matching node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (of_address_to_resource(np, 0, ®s) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pr_err("failed to get FUSE register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) fuse->soc = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) np = of_find_matching_node(NULL, car_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) void __iomem *base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) tegra_enable_fuse_clk(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pr_err("failed to map clock registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fuse->base = ioremap(regs.start, resource_size(®s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!fuse->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pr_err("failed to map FUSE registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) fuse->soc->init(fuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) tegra_revision_name[tegra_sku_info.revision],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) tegra_sku_info.sku_id, tegra_sku_info.cpu_process_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) tegra_sku_info.soc_process_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (fuse->soc->lookups) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) size_t size = sizeof(*fuse->lookups) * fuse->soc->num_lookups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) fuse->lookups = kmemdup(fuse->soc->lookups, size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!fuse->lookups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) early_initcall(tegra_init_fuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int __init tegra_init_soc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct device *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* make sure we're running on Tegra */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) np = of_find_matching_node(NULL, tegra_fuse_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) soc = tegra_soc_device_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (IS_ERR(soc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return PTR_ERR(soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) device_initcall(tegra_init_soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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