^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/soc/tegra/flowctrl.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Functions and macros to control the flowcontroller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <soc/tegra/common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <soc/tegra/flowctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static u8 flowctrl_offset_halt_cpu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) FLOW_CTRL_HALT_CPU0_EVENTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) FLOW_CTRL_HALT_CPU1_EVENTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) FLOW_CTRL_HALT_CPU1_EVENTS + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) FLOW_CTRL_HALT_CPU1_EVENTS + 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static u8 flowctrl_offset_cpu_csr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) FLOW_CTRL_CPU0_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) FLOW_CTRL_CPU1_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) FLOW_CTRL_CPU1_CSR + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) FLOW_CTRL_CPU1_CSR + 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void __iomem *tegra_flowctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void flowctrl_update(u8 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (WARN_ONCE(IS_ERR_OR_NULL(tegra_flowctrl_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "Tegra flowctrl not initialised!\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) writel(value, tegra_flowctrl_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* ensure the update has reached the flow controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) readl_relaxed(tegra_flowctrl_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 flowctrl_read_cpu_csr(unsigned int cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u8 offset = flowctrl_offset_cpu_csr[cpuid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (WARN_ONCE(IS_ERR_OR_NULL(tegra_flowctrl_base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "Tegra flowctrl not initialised!\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return readl(tegra_flowctrl_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void flowctrl_cpu_suspend_enter(unsigned int cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg = flowctrl_read_cpu_csr(cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) switch (tegra_get_chip_id()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case TEGRA20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* clear wfe bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* clear wfi bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* pwr gating on wfe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case TEGRA30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case TEGRA114:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case TEGRA124:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* clear wfe bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* clear wfi bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (tegra_get_chip_id() == TEGRA30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * The wfi doesn't work well on Tegra30 because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * CPU hangs under some odd circumstances after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * power-gating (like memory running off PLLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * hence use wfe that is working perfectly fine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Note that Tegra30 TRM doc clearly stands that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * wfi should be used for the "Cluster Switching",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * while wfe for the power-gating, just like it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * is done on Tegra20.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* pwr gating on wfi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) reg |= TEGRA30_FLOW_CTRL_CSR_WFI_CPU0 << cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg |= FLOW_CTRL_CSR_ENABLE; /* pwr gating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) flowctrl_write_cpu_csr(cpuid, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) for (i = 0; i < num_possible_cpus(); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (i == cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) reg = flowctrl_read_cpu_csr(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) reg |= FLOW_CTRL_CSR_EVENT_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg |= FLOW_CTRL_CSR_INTR_FLAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) flowctrl_write_cpu_csr(i, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void flowctrl_cpu_suspend_exit(unsigned int cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Disable powergating via flow controller for CPU0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) reg = flowctrl_read_cpu_csr(cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) switch (tegra_get_chip_id()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case TEGRA20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* clear wfe bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* clear wfi bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case TEGRA30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case TEGRA114:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case TEGRA124:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* clear wfe bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* clear wfi bitmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reg &= ~TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg &= ~FLOW_CTRL_CSR_ENABLE; /* clear enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) reg |= FLOW_CTRL_CSR_INTR_FLAG; /* clear intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg |= FLOW_CTRL_CSR_EVENT_FLAG; /* clear event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) flowctrl_write_cpu_csr(cpuid, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int tegra_flowctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __iomem *base = tegra_flowctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tegra_flowctrl_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (IS_ERR(tegra_flowctrl_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return PTR_ERR(tegra_flowctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct of_device_id tegra_flowctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .compatible = "nvidia,tegra210-flowctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { .compatible = "nvidia,tegra124-flowctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .compatible = "nvidia,tegra114-flowctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { .compatible = "nvidia,tegra30-flowctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .compatible = "nvidia,tegra20-flowctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct platform_driver tegra_flowctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "tegra-flowctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .of_match_table = tegra_flowctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .probe = tegra_flowctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) builtin_platform_driver(tegra_flowctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int __init tegra_flowctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (!soc_is_tegra())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) np = of_find_matching_node(NULL, tegra_flowctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (of_address_to_resource(np, 0, &res) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pr_err("failed to get flowctrl register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) } else if (IS_ENABLED(CONFIG_ARM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * Hardcoded fallback for 32-bit Tegra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * devices if device tree node is missing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) res.start = 0x60007000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) res.end = 0x60007fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) res.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * At this point we're running on a Tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * that doesn't support the flow controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * (eg. Tegra186), so just return.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) tegra_flowctrl_base = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!tegra_flowctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) early_initcall(tegra_flowctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags