^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) if ARCH_TEGRA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) # 32-bit ARM SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) if ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) config ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) bool "Enable support for Tegra20 family"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) select ARM_ERRATA_720789
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) select ARM_ERRATA_754327 if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) select ARM_ERRATA_764369 if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) select PINCTRL_TEGRA20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) select PL310_ERRATA_727915 if CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) select PL310_ERRATA_769419 if CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) select SOC_TEGRA_FLOWCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) select SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) select SOC_TEGRA20_VOLTAGE_COUPLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) select TEGRA_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Support for NVIDIA Tegra AP20 and T20 processors, based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) config ARCH_TEGRA_3x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) bool "Enable support for Tegra30 family"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) select ARM_ERRATA_754322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) select ARM_ERRATA_764369 if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) select PINCTRL_TEGRA30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) select PL310_ERRATA_769419 if CACHE_L2X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) select SOC_TEGRA_FLOWCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) select SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) select SOC_TEGRA30_VOLTAGE_COUPLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) select TEGRA_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Support for NVIDIA Tegra T30 processor family, based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) config ARCH_TEGRA_114_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool "Enable support for Tegra114 family"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) select ARM_ERRATA_798181 if SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) select HAVE_ARM_ARCH_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) select PINCTRL_TEGRA114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) select SOC_TEGRA_FLOWCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) select SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) select TEGRA_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Support for NVIDIA Tegra T114 processor family, based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ARM CortexA15MP CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) config ARCH_TEGRA_124_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool "Enable support for Tegra124 family"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) select HAVE_ARM_ARCH_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) select PINCTRL_TEGRA124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) select SOC_TEGRA_FLOWCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) select SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) select TEGRA_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Support for NVIDIA Tegra T124 processor family, based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ARM CortexA15MP CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # 64-bit ARM SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) config ARCH_TEGRA_132_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bool "NVIDIA Tegra132 SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) select PINCTRL_TEGRA124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) select SOC_TEGRA_FLOWCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) select SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Enable support for NVIDIA Tegra132 SoC, based on the Denver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) but contains an NVIDIA Denver CPU complex in place of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Tegra124's "4+1" Cortex-A15 CPU complex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) config ARCH_TEGRA_210_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) bool "NVIDIA Tegra210 SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) select PINCTRL_TEGRA210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) select SOC_TEGRA_FLOWCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) select SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) select TEGRA_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) cores in a switched configuration. It features a GPU of the Maxwell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) and providing 256 CUDA cores. It supports hardware-accelerated en-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) and decoding of various video standards including H.265, H.264 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) VP8 at 4K resolution and up to 60 fps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) Besides the multimedia features it also comes with a variety of I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) name only a few.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) config ARCH_TEGRA_186_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool "NVIDIA Tegra186 SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) select MAILBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) select TEGRA_BPMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) select TEGRA_HSP_MBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) select TEGRA_IVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) select SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) combination of Denver and Cortex-A57 CPU cores and a GPU based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) used for audio processing, hardware video encoders/decoders with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) multi-format support, ISP for image capture processing and BPMP for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) power management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) config ARCH_TEGRA_194_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bool "NVIDIA Tegra194 SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) select MAILBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) select PINCTRL_TEGRA194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) select TEGRA_BPMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) select TEGRA_HSP_MBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) select TEGRA_IVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) select SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) Enable support for the NVIDIA Tegra194 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) config ARCH_TEGRA_234_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool "NVIDIA Tegra234 SoC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) select MAILBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) select TEGRA_BPMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) select TEGRA_HSP_MBOX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) select TEGRA_IVC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) select SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) Enable support for the NVIDIA Tegra234 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) config SOC_TEGRA_FUSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) depends on ARCH_TEGRA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) select SOC_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) select TEGRA20_APB_DMA if ARCH_TEGRA_2x_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) config SOC_TEGRA_FLOWCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) config SOC_TEGRA_PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) select GENERIC_PINCONF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) config SOC_TEGRA_POWERGATE_BPMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) depends on PM_GENERIC_DOMAINS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) depends on TEGRA_BPMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) config SOC_TEGRA20_VOLTAGE_COUPLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool "Voltage scaling support for Tegra20 SoCs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) config SOC_TEGRA30_VOLTAGE_COUPLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bool "Voltage scaling support for Tegra30 SoCs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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