^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Allwinner SoCs SRAM Controller Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/soc/sunxi/sunxi_sram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct sunxi_sram_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) char *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct sunxi_sram_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct sunxi_sram_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct sunxi_sram_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct sunxi_sram_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool claimed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUNXI_SRAM_MAP(_reg_val, _val, _func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .func = _func, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .val = _val, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .reg_val = _reg_val, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .offset = _off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .func = (struct sunxi_sram_func[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __VA_ARGS__, { } }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .data = SUNXI_SRAM_DATA("A3-A4", 0x4, 0x4, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SUNXI_SRAM_MAP(0, 0, "cpu"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SUNXI_SRAM_MAP(1, 1, "emac")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SUNXI_SRAM_MAP(0, 0, "cpu"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct sunxi_sram_desc sun4i_a10_sram_d = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SUNXI_SRAM_MAP(0, 0, "cpu"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SUNXI_SRAM_MAP(1, 1, "usb-otg")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct sunxi_sram_desc sun50i_a64_sram_c = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .data = SUNXI_SRAM_DATA("C", 0x4, 24, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) SUNXI_SRAM_MAP(0, 1, "cpu"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SUNXI_SRAM_MAP(1, 0, "de2")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct of_device_id sunxi_sram_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .compatible = "allwinner,sun4i-a10-sram-a3-a4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .data = &sun4i_a10_sram_a3_a4.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .compatible = "allwinner,sun4i-a10-sram-c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .data = &sun4i_a10_sram_c1.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .compatible = "allwinner,sun4i-a10-sram-d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .data = &sun4i_a10_sram_d.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .compatible = "allwinner,sun50i-a64-sram-c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .data = &sun50i_a64_sram_c.data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct device *sram_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static LIST_HEAD(claimed_sram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static DEFINE_SPINLOCK(sram_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int sunxi_sram_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct device_node *sram_node, *section_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const struct sunxi_sram_data *sram_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct sunxi_sram_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const __be32 *sram_addr_p, *section_addr_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) seq_puts(s, "Allwinner sunXi SRAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) seq_puts(s, "--------------------\n\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for_each_child_of_node(sram_dev->of_node, sram_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) seq_printf(s, "sram@%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) be32_to_cpu(*sram_addr_p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) for_each_child_of_node(sram_node, section_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) match = of_match_node(sunxi_sram_dt_ids, section_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) sram_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) section_addr_p = of_get_address(section_node, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) seq_printf(s, "\tsection@%04x\t(%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) be32_to_cpu(*section_addr_p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) sram_data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val = readl(base + sram_data->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val >>= sram_data->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val &= GENMASK(sram_data->width - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (func = sram_data->func; func->func; func++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) seq_printf(s, "\t\t%s%c\n", func->func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) func->reg_val == val ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) '*' : ' ');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) seq_puts(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DEFINE_SHOW_ATTRIBUTE(sunxi_sram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline struct sunxi_sram_desc *to_sram_desc(const struct sunxi_sram_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return container_of(data, struct sunxi_sram_desc, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct sunxi_sram_data *sunxi_sram_of_parse(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned int *reg_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const struct sunxi_sram_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct sunxi_sram_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct of_phandle_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = of_parse_phandle_with_fixed_args(node, "allwinner,sram", 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!of_device_is_available(args.np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val = args.args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) match = of_match_node(sunxi_sram_dt_ids, args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) for (func = data->func; func->func; func++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (val == func->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (reg_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *reg_value = func->reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!func->func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) of_node_put(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) of_node_put(args.np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int sunxi_sram_claim(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const struct sunxi_sram_data *sram_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct sunxi_sram_desc *sram_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned int device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!dev || !dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) sram_data = sunxi_sram_of_parse(dev->of_node, &device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (IS_ERR(sram_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return PTR_ERR(sram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) sram_desc = to_sram_desc(sram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) spin_lock(&sram_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (sram_desc->claimed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) spin_unlock(&sram_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mask = GENMASK(sram_data->offset + sram_data->width - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) sram_data->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) val = readl(base + sram_data->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writel(val | ((device << sram_data->offset) & mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) base + sram_data->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) spin_unlock(&sram_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EXPORT_SYMBOL(sunxi_sram_claim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int sunxi_sram_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) const struct sunxi_sram_data *sram_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct sunxi_sram_desc *sram_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!dev || !dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) sram_data = sunxi_sram_of_parse(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (IS_ERR(sram_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sram_desc = to_sram_desc(sram_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_lock(&sram_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) sram_desc->claimed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) spin_unlock(&sram_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) EXPORT_SYMBOL(sunxi_sram_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct sunxi_sramc_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bool has_emac_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Nothing special */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .has_emac_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .has_emac_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (reg == SUNXI_SRAM_EMAC_CLOCK_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct regmap_config sunxi_sram_emac_clock_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* last defined register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .max_register = SUNXI_SRAM_EMAC_CLOCK_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* other devices have no business accessing other registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .readable_reg = sunxi_sram_regmap_accessible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .writeable_reg = sunxi_sram_regmap_accessible_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int sunxi_sram_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct dentry *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct regmap *emac_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const struct sunxi_sramc_variant *variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) sram_dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) variant = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!variant)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) d = debugfs_create_file("sram", S_IRUGO, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) &sunxi_sram_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (variant->has_emac_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) emac_clock = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &sunxi_sram_emac_clock_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (IS_ERR(emac_clock))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return PTR_ERR(emac_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct of_device_id sunxi_sram_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .compatible = "allwinner,sun4i-a10-sram-controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .data = &sun4i_a10_sramc_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .compatible = "allwinner,sun4i-a10-system-control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .data = &sun4i_a10_sramc_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .compatible = "allwinner,sun5i-a13-system-control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .data = &sun4i_a10_sramc_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .compatible = "allwinner,sun8i-a23-system-control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .data = &sun4i_a10_sramc_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .compatible = "allwinner,sun8i-h3-system-control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .data = &sun8i_h3_sramc_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .compatible = "allwinner,sun50i-a64-sram-controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .data = &sun50i_a64_sramc_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .compatible = "allwinner,sun50i-a64-system-control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .data = &sun50i_a64_sramc_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .compatible = "allwinner,sun50i-h5-system-control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .data = &sun50i_a64_sramc_variant,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static struct platform_driver sunxi_sram_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .name = "sunxi-sram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .of_match_table = sunxi_sram_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .probe = sunxi_sram_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) module_platform_driver(sunxi_sram_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_DESCRIPTION("Allwinner sunXi SRAM Controller Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags