Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Copyright (C) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) //	Tomasz Figa <t.figa@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) // Copyright (C) 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) // Copyright (C) 2004-2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) //	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) //	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Samsung common power management (suspend to RAM) debug support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/soc/samsung/s3c-pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct pm_uart_save uart_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern void printascii(const char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void s3c_pm_dbg(const char *fmt, ...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	va_list va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	char buff[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	va_start(va, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	vsnprintf(buff, sizeof(buff), fmt, va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	va_end(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	printascii(buff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static inline void __iomem *s3c_pm_uart_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	unsigned long paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	unsigned long vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	debug_ll_addr(&paddr, &vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	return (void __iomem *)vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void s3c_pm_save_uarts(bool is_s3c2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	void __iomem *regs = s3c_pm_uart_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	struct pm_uart_save *save = &uart_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	save->ulcon = __raw_readl(regs + S3C2410_ULCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	save->ucon = __raw_readl(regs + S3C2410_UCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	save->ufcon = __raw_readl(regs + S3C2410_UFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	save->umcon = __raw_readl(regs + S3C2410_UMCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	if (!is_s3c2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	S3C_PMDBG("UART[%p]: ULCON=%04x, UCON=%04x, UFCON=%04x, UBRDIV=%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		  regs, save->ulcon, save->ucon, save->ufcon, save->ubrdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void s3c_pm_restore_uarts(bool is_s3c2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	void __iomem *regs = s3c_pm_uart_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	struct pm_uart_save *save = &uart_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	s3c_pm_arch_update_uart(regs, save);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	__raw_writel(save->ulcon, regs + S3C2410_ULCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	__raw_writel(save->ucon,  regs + S3C2410_UCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	__raw_writel(save->ufcon, regs + S3C2410_UFCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	__raw_writel(save->umcon, regs + S3C2410_UMCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	__raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	if (!is_s3c2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		__raw_writel(save->udivslot, regs + S3C2443_DIVSLOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }