^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip PVTM support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Finley Xiao <finley.xiao@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/soc/rockchip/pvtm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define wr_mask_bit(v, off, mask) ((v) << (off) | (mask) << (16 + off))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PVTM(_id, _name, _num_rings, _start, _en, _cal, _done, _freq) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .num_rings = _num_rings, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .bit_start = _start, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .bit_en = _en, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .reg_cal = _cal, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .bit_freq_done = _done, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .reg_freq = _freq, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct rockchip_pvtm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct rockchip_pvtm_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 (*get_value)(struct rockchip_pvtm *pvtm, unsigned int ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int time_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void (*set_ring_sel)(struct rockchip_pvtm *pvtm, unsigned int ring_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct rockchip_pvtm_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 reg_cal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 reg_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned char id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int num_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int bit_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int bit_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int bit_freq_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct rockchip_pvtm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int num_pvtms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const struct rockchip_pvtm_info *infos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const struct rockchip_pvtm_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct rockchip_pvtm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct thermal_zone_device *tz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct rockchip_pvtm_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const struct rockchip_pvtm_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct dentry *dentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static LIST_HEAD(pvtm_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct dentry *rockchip_pvtm_debugfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int pvtm_value_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct rockchip_pvtm *pvtm = (struct rockchip_pvtm *)s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int i, ret, cur_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!pvtm || !pvtm->ops->get_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) seq_puts(s, "unsupported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (pvtm->tz && pvtm->tz->ops && pvtm->tz->ops->get_temp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = pvtm->tz->ops->get_temp(pvtm->tz, &cur_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_err(pvtm->dev, "debug failed to get temp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) seq_printf(s, "temp: %d ", cur_temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) seq_puts(s, "pvtm: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) for (i = 0; i < pvtm->info->num_rings; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) value = pvtm->ops->get_value(pvtm, i, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) seq_printf(s, "%d ", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) seq_puts(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int pvtm_value_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return single_open(file, pvtm_value_show, inode->i_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct file_operations pvtm_value_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .open = pvtm_value_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .read = seq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .llseek = seq_lseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .release = single_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int rockchip_pvtm_debugfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rockchip_pvtm_debugfs_root = debugfs_create_dir("pvtm", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (IS_ERR_OR_NULL(rockchip_pvtm_debugfs_root)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pr_err("Failed to create pvtm debug directory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) rockchip_pvtm_debugfs_root = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void rockchip_pvtm_debugfs_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) debugfs_remove_recursive(rockchip_pvtm_debugfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int rockchip_pvtm_add_debugfs(struct rockchip_pvtm *pvtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct dentry *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (!rockchip_pvtm_debugfs_root)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pvtm->dentry = debugfs_create_dir(pvtm->info->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) rockchip_pvtm_debugfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (!pvtm->dentry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_err(pvtm->dev, "failed to create pvtm %s debug dir\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pvtm->info->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) d = debugfs_create_file("value", 0444, pvtm->dentry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) (void *)pvtm, &pvtm_value_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (!d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(pvtm->dev, "failed to pvtm %s value node\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) pvtm->info->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) debugfs_remove_recursive(pvtm->dentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline int rockchip_pvtm_debugfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline void rockchip_pvtm_debugfs_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline int rockchip_pvtm_add_debugfs(struct rockchip_pvtm *pvtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int rockchip_pvtm_reset(struct rockchip_pvtm *pvtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ret = reset_control_assert(pvtm->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dev_err(pvtm->dev, "failed to assert pvtm %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = reset_control_deassert(pvtm->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(pvtm->dev, "failed to deassert pvtm %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 rockchip_get_pvtm_value(unsigned int id, unsigned int ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int time_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct rockchip_pvtm *p, *pvtm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (list_empty(&pvtm_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_err("pvtm list NULL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) list_for_each_entry(p, &pvtm_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (p->info->id == id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pvtm = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!pvtm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pr_err("invalid pvtm id %d\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (ring_sel >= pvtm->info->num_rings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pr_err("invalid pvtm ring %d\n", ring_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return pvtm->ops->get_value(pvtm, ring_sel, time_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) EXPORT_SYMBOL(rockchip_get_pvtm_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void rockchip_pvtm_delay(unsigned int delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned int ms = delay / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int us = delay % 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ms > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ms < 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) us += ms * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) msleep(ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (us >= 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) usleep_range(us, us + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) udelay(us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void px30_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int ring_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int id = pvtm->info->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) regmap_write(pvtm->grf, pvtm->con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) wr_mask_bit(ring_sel, (id * 0x4 + 0x2), 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void rk1808_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int ring_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) regmap_write(pvtm->grf, pvtm->con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) wr_mask_bit(ring_sel, 0x2, 0x7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void rk3399_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int ring_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int id = pvtm->info->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (id == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) regmap_write(pvtm->grf, pvtm->con + 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) wr_mask_bit(ring_sel >> 0x3, 0, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ring_sel &= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (id != 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) regmap_write(pvtm->grf, pvtm->con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) wr_mask_bit(ring_sel, (id * 0x4 + 0x2), 0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static u32 rockchip_pvtm_get_value(struct rockchip_pvtm *pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned int ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned int time_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) const struct rockchip_pvtm_info *info = pvtm->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned int clk_cnt, check_cnt = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 sta, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ret = clk_bulk_prepare_enable(pvtm->num_clks, pvtm->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dev_err(pvtm->dev, "failed to prepare/enable pvtm clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret = rockchip_pvtm_reset(pvtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(pvtm->dev, "failed to reset pvtm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* if last status is enabled, stop calculating cycles first*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regmap_read(pvtm->grf, pvtm->con, &sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (sta & BIT(info->bit_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regmap_write(pvtm->grf, pvtm->con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) wr_mask_bit(0, info->bit_start, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) regmap_write(pvtm->grf, pvtm->con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) wr_mask_bit(0x1, info->bit_en, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (pvtm->ops->set_ring_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pvtm->ops->set_ring_sel(pvtm, ring_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* clk = 24 Mhz, T = 1 / 24 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) clk_cnt = time_us * 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) regmap_write(pvtm->grf, pvtm->con + info->reg_cal, clk_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) regmap_write(pvtm->grf, pvtm->con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) wr_mask_bit(0x1, info->bit_start, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) rockchip_pvtm_delay(time_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) while (check_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) regmap_read(pvtm->grf, pvtm->sta, &sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (sta & BIT(info->bit_freq_done))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) udelay(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) check_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (check_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) regmap_read(pvtm->grf, pvtm->sta + info->reg_freq, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(pvtm->dev, "wait pvtm_done timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) regmap_write(pvtm->grf, pvtm->con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) wr_mask_bit(0, info->bit_start, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) regmap_write(pvtm->grf, pvtm->con,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) wr_mask_bit(0, info->bit_en, 0x1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) clk_bulk_disable_unprepare(pvtm->num_clks, pvtm->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void rv1106_core_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned int ring_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) writel_relaxed(wr_mask_bit(ring_sel + 4, 0x2, 0x7), pvtm->base + pvtm->con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void rv1126_pvtm_set_ring_sel(struct rockchip_pvtm *pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int ring_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) writel_relaxed(wr_mask_bit(ring_sel, 0x2, 0x7), pvtm->base + pvtm->con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static u32 rv1126_pvtm_get_value(struct rockchip_pvtm *pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned int time_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) const struct rockchip_pvtm_info *info = pvtm->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned int clk_cnt, check_cnt = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 sta, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = clk_bulk_prepare_enable(pvtm->num_clks, pvtm->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_err(pvtm->dev, "failed to prepare/enable pvtm clks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = rockchip_pvtm_reset(pvtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_err(pvtm->dev, "failed to reset pvtm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) goto disable_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* if last status is enabled, stop calculating cycles first*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sta = readl_relaxed(pvtm->base + pvtm->con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (sta & BIT(info->bit_en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel_relaxed(wr_mask_bit(0, info->bit_start, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pvtm->base + pvtm->con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) writel_relaxed(wr_mask_bit(0x1, info->bit_en, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pvtm->base + pvtm->con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (pvtm->ops->set_ring_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pvtm->ops->set_ring_sel(pvtm, ring_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* clk = 24 Mhz, T = 1 / 24 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) clk_cnt = time_us * 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) writel_relaxed(clk_cnt, pvtm->base + pvtm->con + info->reg_cal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) writel_relaxed(wr_mask_bit(0x1, info->bit_start, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pvtm->base + pvtm->con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rockchip_pvtm_delay(time_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) while (check_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) sta = readl_relaxed(pvtm->base + pvtm->sta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (sta & BIT(info->bit_freq_done))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) udelay(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) check_cnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (check_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) val = readl_relaxed(pvtm->base + pvtm->sta + info->reg_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_err(pvtm->dev, "wait pvtm_done timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel_relaxed(wr_mask_bit(0, info->bit_start, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pvtm->base + pvtm->con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) writel_relaxed(wr_mask_bit(0, info->bit_en, 0x1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pvtm->base + pvtm->con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) disable_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) clk_bulk_disable_unprepare(pvtm->num_clks, pvtm->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct rockchip_pvtm_info px30_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PVTM(0, "core", 3, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const struct rockchip_pvtm_data px30_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .con = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .sta = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .num_pvtms = ARRAY_SIZE(px30_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .infos = px30_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .get_value = rockchip_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .set_ring_sel = px30_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const struct rockchip_pvtm_info px30_pmupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PVTM(1, "pmu", 1, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct rockchip_pvtm_data px30_pmupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .con = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .sta = 0x190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .num_pvtms = ARRAY_SIZE(px30_pmupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .infos = px30_pmupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .get_value = rockchip_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct rockchip_pvtm_info rk1808_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PVTM(0, "core", 5, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct rockchip_pvtm_data rk1808_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .con = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .sta = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .num_pvtms = ARRAY_SIZE(rk1808_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .infos = rk1808_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .get_value = rockchip_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .set_ring_sel = rk1808_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct rockchip_pvtm_info rk1808_pmupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PVTM(1, "pmu", 1, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct rockchip_pvtm_data rk1808_pmupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .con = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .sta = 0x190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .num_pvtms = ARRAY_SIZE(rk1808_pmupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .infos = rk1808_pmupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .get_value = rockchip_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const struct rockchip_pvtm_info rk1808_npupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PVTM(2, "npu", 5, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct rockchip_pvtm_data rk1808_npupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .con = 0x780,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .sta = 0x788,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .num_pvtms = ARRAY_SIZE(rk1808_npupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .infos = rk1808_npupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .get_value = rockchip_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .set_ring_sel = rk1808_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct rockchip_pvtm_info rk3288_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PVTM(0, "core", 1, 0, 1, 0x4, 1, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PVTM(1, "gpu", 1, 8, 9, 0x8, 0, 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct rockchip_pvtm_data rk3288_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .con = 0x368,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .sta = 0x374,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .num_pvtms = ARRAY_SIZE(rk3288_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .infos = rk3288_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .get_value = rockchip_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct rockchip_pvtm_data rk3308_pmupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .con = 0x440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .sta = 0x448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .num_pvtms = ARRAY_SIZE(px30_pmupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .infos = px30_pmupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .get_value = rockchip_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const struct rockchip_pvtm_info rk3399_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PVTM(0, "core_l", 4, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PVTM(1, "core_b", 6, 4, 5, 0x8, 1, 0x8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PVTM(2, "ddr", 4, 8, 9, 0xc, 3, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PVTM(3, "gpu", 4, 12, 13, 0x10, 2, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const struct rockchip_pvtm_data rk3399_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .con = 0xe600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .sta = 0xe620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .num_pvtms = ARRAY_SIZE(rk3399_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .infos = rk3399_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .get_value = rockchip_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .set_ring_sel = rk3399_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct rockchip_pvtm_info rk3399_pmupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PVTM(4, "pmu", 1, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const struct rockchip_pvtm_data rk3399_pmupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .con = 0x240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .sta = 0x248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .num_pvtms = ARRAY_SIZE(rk3399_pmupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .infos = rk3399_pmupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .get_value = rockchip_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const struct rockchip_pvtm_info rk3568_corepvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PVTM(0, "core", 7, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct rockchip_pvtm_data rk3568_corepvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .num_pvtms = ARRAY_SIZE(rk3568_corepvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .infos = rk3568_corepvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct rockchip_pvtm_info rk3568_gpupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PVTM(1, "gpu", 7, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const struct rockchip_pvtm_data rk3568_gpupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .num_pvtms = ARRAY_SIZE(rk3568_gpupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .infos = rk3568_gpupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const struct rockchip_pvtm_info rk3568_npupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PVTM(2, "npu", 7, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const struct rockchip_pvtm_data rk3568_npupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .num_pvtms = ARRAY_SIZE(rk3568_npupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .infos = rk3568_npupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct rockchip_pvtm_info rk3588_bigcore0_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PVTM(0, "bigcore0", 7, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const struct rockchip_pvtm_data rk3588_bigcore0_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .num_pvtms = ARRAY_SIZE(rk3588_bigcore0_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .infos = rk3588_bigcore0_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const struct rockchip_pvtm_info rk3588_bigcore1_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PVTM(1, "bigcore1", 7, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const struct rockchip_pvtm_data rk3588_bigcore1_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .num_pvtms = ARRAY_SIZE(rk3588_bigcore1_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .infos = rk3588_bigcore1_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const struct rockchip_pvtm_info rk3588_litcore_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PVTM(2, "litcore", 7, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct rockchip_pvtm_data rk3588_litcore_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .num_pvtms = ARRAY_SIZE(rk3588_litcore_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .infos = rk3588_litcore_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const struct rockchip_pvtm_info rk3588_npu_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PVTM(3, "npu", 2, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const struct rockchip_pvtm_data rk3588_npu_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .num_pvtms = ARRAY_SIZE(rk3588_npu_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .infos = rk3588_npu_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const struct rockchip_pvtm_info rk3588_gpu_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PVTM(4, "gpu", 2, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct rockchip_pvtm_data rk3588_gpu_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .num_pvtms = ARRAY_SIZE(rk3588_gpu_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .infos = rk3588_gpu_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const struct rockchip_pvtm_info rk3588_pmu_pvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PVTM(5, "pmu", 1, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const struct rockchip_pvtm_data rk3588_pmu_pvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .num_pvtms = ARRAY_SIZE(rk3588_pmu_pvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .infos = rk3588_pmu_pvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const struct rockchip_pvtm_info rv1106_corepvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PVTM(0, "core", 2, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const struct rockchip_pvtm_data rv1106_corepvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .num_pvtms = ARRAY_SIZE(rv1106_corepvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .infos = rv1106_corepvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .set_ring_sel = rv1106_core_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const struct rockchip_pvtm_info rv1106_pmupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PVTM(1, "pmu", 1, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const struct rockchip_pvtm_data rv1106_pmupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .num_pvtms = ARRAY_SIZE(rv1106_pmupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .infos = rv1106_pmupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const struct rockchip_pvtm_info rv1126_cpupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PVTM(0, "cpu", 7, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const struct rockchip_pvtm_data rv1126_cpupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .num_pvtms = ARRAY_SIZE(rv1126_cpupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .infos = rv1126_cpupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const struct rockchip_pvtm_info rv1126_npupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PVTM(1, "npu", 7, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const struct rockchip_pvtm_data rv1126_npupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .num_pvtms = ARRAY_SIZE(rv1126_npupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .infos = rv1126_npupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .set_ring_sel = rv1126_pvtm_set_ring_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static const struct rockchip_pvtm_info rv1126_pmupvtm_infos[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PVTM(2, "pmu", 1, 0, 1, 0x4, 0, 0x4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct rockchip_pvtm_data rv1126_pmupvtm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .con = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .sta = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .num_pvtms = ARRAY_SIZE(rv1126_pmupvtm_infos),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .infos = rv1126_pmupvtm_infos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .get_value = rv1126_pvtm_get_value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct of_device_id rockchip_pvtm_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #ifdef CONFIG_CPU_PX30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .compatible = "rockchip,px30-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .data = (void *)&px30_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .compatible = "rockchip,px30-pmu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .data = (void *)&px30_pmupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #ifdef CONFIG_CPU_RK1808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .compatible = "rockchip,rk1808-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .data = (void *)&rk1808_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .compatible = "rockchip,rk1808-pmu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .data = (void *)&rk1808_pmupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .compatible = "rockchip,rk1808-npu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .data = (void *)&rk1808_npupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #ifdef CONFIG_CPU_RK3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .compatible = "rockchip,rk3288-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .data = (void *)&rk3288_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #ifdef CONFIG_CPU_RK3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .compatible = "rockchip,rk3308-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .data = (void *)&px30_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .compatible = "rockchip,rk3308-pmu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .data = (void *)&rk3308_pmupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #ifdef CONFIG_CPU_RK3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .compatible = "rockchip,rk3399-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .data = (void *)&rk3399_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .compatible = "rockchip,rk3399-pmu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .data = (void *)&rk3399_pmupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #ifdef CONFIG_CPU_RK3568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .compatible = "rockchip,rK3568-core-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .data = (void *)&rk3568_corepvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .compatible = "rockchip,rk3568-gpu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .data = (void *)&rk3568_gpupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .compatible = "rockchip,rk3568-npu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .data = (void *)&rk3568_npupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #ifdef CONFIG_CPU_RK3588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .compatible = "rockchip,rk3588-bigcore0-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .data = (void *)&rk3588_bigcore0_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .compatible = "rockchip,rk3588-bigcore1-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .data = (void *)&rk3588_bigcore1_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .compatible = "rockchip,rk3588-litcore-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .data = (void *)&rk3588_litcore_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .compatible = "rockchip,rk3588-gpu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .data = (void *)&rk3588_gpu_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .compatible = "rockchip,rk3588-npu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .data = (void *)&rk3588_npu_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .compatible = "rockchip,rk3588-pmu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .data = (void *)&rk3588_pmu_pvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #ifdef CONFIG_CPU_RV1106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .compatible = "rockchip,rv1106-core-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .data = (void *)&rv1106_corepvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .compatible = "rockchip,rv1106-pmu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .data = (void *)&rv1106_pmupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #ifdef CONFIG_CPU_RV1126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .compatible = "rockchip,rv1126-cpu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .data = (void *)&rv1126_cpupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .compatible = "rockchip,rv1126-npu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .data = (void *)&rv1126_npupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .compatible = "rockchip,rv1126-pmu-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .data = (void *)&rv1126_pmupvtm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) MODULE_DEVICE_TABLE(of, rockchip_pvtm_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static int rockchip_pvtm_get_index(const struct rockchip_pvtm_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u32 ch, u32 *index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) for (i = 0; i < data->num_pvtms; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (ch == data->infos[i].id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) *index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static struct rockchip_pvtm *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) rockchip_pvtm_init(struct device *dev, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) const struct rockchip_pvtm_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct regmap *grf, void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct rockchip_pvtm *pvtm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) const char *tz_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 id, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (of_property_read_u32(node, "reg", &id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_err(dev, "%s: failed to retrieve pvtm id\n", node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (rockchip_pvtm_get_index(data, id, &index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) dev_err(dev, "%s: invalid pvtm id %d\n", node->name, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) pvtm = devm_kzalloc(dev, sizeof(*pvtm), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!pvtm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) pvtm->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) pvtm->grf = grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pvtm->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) pvtm->con = data->con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pvtm->sta = data->sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) pvtm->ops = &data->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) pvtm->info = &data->infos[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (!of_property_read_string(node, "thermal-zone", &tz_name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) pvtm->tz = thermal_zone_get_zone_by_name(tz_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (IS_ERR(pvtm->tz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) dev_err(pvtm->dev, "failed to retrieve pvtm_tz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) pvtm->tz = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pvtm->num_clks = of_clk_get_parent_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (pvtm->num_clks <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_err(dev, "%s: does not have clocks\n", node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) goto clk_num_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) pvtm->clks = devm_kcalloc(dev, pvtm->num_clks, sizeof(*pvtm->clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (!pvtm->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) goto clk_num_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) for (i = 0; i < pvtm->num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pvtm->clks[i].clk = of_clk_get(node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (IS_ERR(pvtm->clks[i].clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_err(dev, "%s: failed to get clk at index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) node->name, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) pvtm->rst = devm_reset_control_array_get_optional_exclusive(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (IS_ERR(pvtm->rst))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) dev_dbg(dev, "%s: failed to get reset\n", node->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) rockchip_pvtm_add_debugfs(pvtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return pvtm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) clk_put(pvtm->clks[i].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) devm_kfree(dev, pvtm->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) clk_num_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) devm_kfree(dev, pvtm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int rockchip_pvtm_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct rockchip_pvtm *pvtm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct regmap *grf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) void __iomem *base = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) match = of_match_device(dev->driver->of_match_table, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!match || !match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dev_err(dev, "missing pvtm data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (dev->parent && dev->parent->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) grf = syscon_node_to_regmap(dev->parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (IS_ERR(grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return PTR_ERR(grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) for_each_available_child_of_node(np, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) pvtm = rockchip_pvtm_init(dev, node, match->data, grf, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (!pvtm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_err(dev, "failed to handle node %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) node->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) list_add(&pvtm->node, &pvtm_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dev_info(dev, "%s probed\n", node->full_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static struct platform_driver rockchip_pvtm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .probe = rockchip_pvtm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .name = "rockchip-pvtm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .of_match_table = rockchip_pvtm_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int __init rockchip_pvtm_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) rockchip_pvtm_debugfs_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return platform_driver_register(&rockchip_pvtm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) module_init(rockchip_pvtm_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static void __exit rockchip_pvtm_module_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) rockchip_pvtm_debugfs_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) platform_driver_unregister(&rockchip_pvtm_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) module_exit(rockchip_pvtm_module_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) MODULE_DESCRIPTION("Rockchip PVTM driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) MODULE_AUTHOR("Finley Xiao <finley.xiao@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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