Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier:     GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2020 Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/initramfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/soc/rockchip/rockchip_decompress.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DECOM_CTRL		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DECOM_ENR		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DECOM_RADDR		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DECOM_WADDR		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DECOM_UDDSL		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DECOM_UDDSH		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DECOM_TXTHR		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DECOM_RXTHR		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define DECOM_SLEN		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DECOM_STAT		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DECOM_ISR		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DECOM_IEN		0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DECOM_AXI_STAT		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DECOM_TSIZEL		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DECOM_TSIZEH		0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DECOM_MGNUM		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DECOM_FRAME		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define DECOM_DICTID		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DECOM_CSL		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DECOM_CSH		0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DECOM_LMTSL		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DECOM_LMTSH		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define LZ4_HEAD_CSUM_CHECK_EN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define LZ4_BLOCK_CSUM_CHECK_EN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define LZ4_CONT_CSUM_CHECK_EN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DSOLIEN			BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ZDICTEIEN		BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define GCMEIEN			BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define GIDEIEN			BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CCCEIEN			BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define BCCEIEN			BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define HCCEIEN			BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CSEIEN			BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define DICTEIEN		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define VNEIEN			BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define WNEIEN			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define RDCEIEN			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define WRCEIEN			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DISEIEN			BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define LENEIEN			BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define LITEIEN			BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SQMEIEN			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SLCIEN			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define HDEIEN			BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DSIEN			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define DECOM_STOP		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define DECOM_COMPLETE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define DECOM_GZIP_MODE		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DECOM_ZLIB_MODE		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define DECOM_DEFLATE_MODE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DECOM_ENABLE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DECOM_DISABLE		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DECOM_INT_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	(DSOLIEN | ZDICTEIEN | GCMEIEN | GIDEIEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	CCCEIEN | BCCEIEN | HCCEIEN | CSEIEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	DICTEIEN | VNEIEN | WNEIEN | RDCEIEN | WRCEIEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	DISEIEN | LENEIEN | LITEIEN | SQMEIEN | SLCIEN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	HDEIEN | DSIEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct rk_decom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int num_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct clk_bulk_data *clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	phys_addr_t mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	size_t mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static struct rk_decom *g_decom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static DECLARE_WAIT_QUEUE_HEAD(g_decom_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static bool g_decom_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static bool g_decom_noblocking;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static u64 g_decom_data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __init wait_initrd_hw_decom_done(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	wait_event(g_decom_wait, g_decom_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int rk_decom_wait_done(u32 timeout, u64 *decom_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (!decom_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	ret = wait_event_timeout(g_decom_wait, g_decom_complete, timeout * HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		if (g_decom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			clk_bulk_disable_unprepare(g_decom->num_clocks, g_decom->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	*decom_len = g_decom_data_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) EXPORT_SYMBOL(rk_decom_wait_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static DECLARE_WAIT_QUEUE_HEAD(decom_init_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int rk_decom_start(u32 mode, phys_addr_t src, phys_addr_t dst, u32 dst_max_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32 decom_enr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32 decom_mode = rk_get_decom_mode(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	wait_event_timeout(decom_init_done, g_decom, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (!g_decom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (g_decom->mem_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		pr_info("%s: mode %u src %pa dst %pa max_size %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			__func__, mode, &src, &dst, dst_max_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	ret = clk_bulk_prepare_enable(g_decom->num_clocks, g_decom->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	g_decom_complete   = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	g_decom_data_len   = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	g_decom_noblocking = rk_get_noblocking_flag(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	decom_enr = readl(g_decom->regs + DECOM_ENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	if (decom_enr & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		pr_err("decompress busy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (g_decom->reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		reset_control_assert(g_decom->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		reset_control_deassert(g_decom->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	irq_status = readl(g_decom->regs + DECOM_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		writel(irq_status, g_decom->regs + DECOM_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	switch (decom_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case LZ4_MOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		writel(LZ4_CONT_CSUM_CHECK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		       LZ4_HEAD_CSUM_CHECK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		       LZ4_BLOCK_CSUM_CHECK_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		       LZ4_MOD, g_decom->regs + DECOM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case GZIP_MOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		writel(DECOM_DEFLATE_MODE | DECOM_GZIP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		       g_decom->regs + DECOM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	case ZLIB_MOD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		writel(DECOM_DEFLATE_MODE | DECOM_ZLIB_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		       g_decom->regs + DECOM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		pr_err("undefined mode : %d\n", decom_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	writel(src, g_decom->regs + DECOM_RADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	writel(dst, g_decom->regs + DECOM_WADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	writel(dst_max_size, g_decom->regs + DECOM_LMTSL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	writel(0x0, g_decom->regs + DECOM_LMTSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	writel(DECOM_INT_MASK, g_decom->regs + DECOM_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	writel(DECOM_ENABLE, g_decom->regs + DECOM_ENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	clk_bulk_disable_unprepare(g_decom->num_clocks, g_decom->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) EXPORT_SYMBOL(rk_decom_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static irqreturn_t rk_decom_irq_handler(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct rk_decom *rk_dec = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	u32 decom_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	irq_status = readl(rk_dec->regs + DECOM_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	writel(irq_status, rk_dec->regs + DECOM_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (irq_status & DECOM_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		decom_status = readl(rk_dec->regs + DECOM_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		if (decom_status & DECOM_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			g_decom_complete = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			g_decom_data_len = readl(rk_dec->regs + DECOM_TSIZEH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			g_decom_data_len = (g_decom_data_len << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 					   readl(rk_dec->regs + DECOM_TSIZEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			wake_up(&g_decom_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			if (rk_dec->mem_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 				dev_info(rk_dec->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					 "decom completed, decom_data_len = %llu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 					 g_decom_data_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			dev_info(rk_dec->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				 "decom failed, irq_status = 0x%x, decom_status = 0x%x, try again !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 				 irq_status, decom_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 				       32, 4, rk_dec->regs, 0x128, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			if (g_decom_noblocking) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				dev_info(rk_dec->dev, "decom failed and exit in noblocking mode.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				writel(DECOM_DISABLE, rk_dec->regs + DECOM_ENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				writel(0, g_decom->regs + DECOM_IEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				g_decom_complete  = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				g_decom_data_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				g_decom_noblocking = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				wake_up(&g_decom_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				writel(DECOM_ENABLE, rk_dec->regs + DECOM_ENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static irqreturn_t rk_decom_irq_thread(int irq, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct rk_decom *rk_dec = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (g_decom_complete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		void *start, *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		if (rk_dec->mem_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			 * Now it is safe to free reserve memory that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			 * store the origin ramdisk file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			start = phys_to_virt(rk_dec->mem_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			end = start + rk_dec->mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			free_reserved_area(start, end, -1, "ramdisk gzip archive");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			rk_dec->mem_start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		clk_bulk_disable_unprepare(rk_dec->num_clocks, rk_dec->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int __init rockchip_decom_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	struct rk_decom *rk_dec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct resource *res = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct device_node *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	struct resource reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	rk_dec = devm_kzalloc(dev, sizeof(*rk_dec), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (!rk_dec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	rk_dec->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	rk_dec->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (rk_dec->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		dev_err(dev, "failed to get rk_dec irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	mem = of_parse_phandle(np, "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (!mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		dev_err(dev, "missing \"memory-region\" property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ret = of_address_to_resource(mem, 0, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	of_node_put(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		dev_err(dev, "missing \"reg\" property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	rk_dec->mem_start = reg.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	rk_dec->mem_size = resource_size(&reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	rk_dec->num_clocks = devm_clk_bulk_get_all(dev, &rk_dec->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (rk_dec->num_clocks < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		dev_err(dev, "failed to get decompress clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	rk_dec->regs = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (IS_ERR(rk_dec->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		ret = PTR_ERR(rk_dec->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	dev_set_drvdata(dev, rk_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	rk_dec->reset = devm_reset_control_get_exclusive(dev, "dresetn");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (IS_ERR(rk_dec->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		ret = PTR_ERR(rk_dec->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		if (ret != -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		dev_dbg(dev, "no reset control found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		rk_dec->reset = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	ret = devm_request_threaded_irq(dev, rk_dec->irq, rk_decom_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 					rk_decom_irq_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 					dev_name(dev), rk_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		dev_err(dev, "failed to attach decompress irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	g_decom = rk_dec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	wake_up(&decom_init_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	clk_bulk_disable_unprepare(rk_dec->num_clocks, rk_dec->clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct of_device_id rockchip_decom_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	{ .compatible = "rockchip,hw-decompress" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct platform_driver rk_decom_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		.name	= "rockchip_hw_decompress",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.of_match_table = rockchip_decom_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int __init rockchip_hw_decompress_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	node = of_find_matching_node(NULL, rockchip_decom_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		of_platform_device_create(node, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		return platform_driver_probe(&rk_decom_driver, rockchip_decom_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pure_initcall(rockchip_hw_decompress_init);