^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/soc/rockchip/rockchip_debug.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Arm debug driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2019 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* RK3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * debug {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * compatible = "rockchip,debug";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * reg = <0x0 0xfe430000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * <0x0 0xfe432000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * <0x0 0xfe434000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * <0x0 0xfe436000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * <0x0 0xfe610000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * <0x0 0xfe710000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* RK3326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * debug {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * compatible = "rockchip,debug";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * reg = <0x0 0xff690000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * <0x0 0xff692000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * <0x0 0xff694000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * <0x0 0xff696000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* RK3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * debug {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * compatible = "rockchip,debug";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * reg = <0x0 0xff810000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * <0x0 0xff812000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * <0x0 0xff814000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * <0x0 0xff816000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* RK3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * debug {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * compatible = "rockchip,debug";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * reg = <0x0 0xffbb0000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * <0x0 0xffbb2000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * <0x0 0xffbb4000 0x0 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * <0x0 0xffbb6000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include "../../staging/android/fiq_debugger/fiq_debugger_priv.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include "rockchip_debug.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EDPCSR_LO 0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EDPCSR_HI 0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EDLAR 0xfb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EDLAR_UNLOCK 0xc5acce55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EDPRSR 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EDPRSR_PU 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EDDEVID 0xFC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PMPCSR_LO 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PMPCSR_HI 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define NUM_CPU_SAMPLES 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NUM_SAMPLES_TO_PRINT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void __iomem *rockchip_cpu_debug[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void __iomem *rockchip_cs_pmu[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static bool edpcsr_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static char log_buf[1024];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern struct atomic_notifier_head hardlock_notifier_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern struct atomic_notifier_head rcu_stall_notifier_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #if IS_ENABLED(CONFIG_FIQ_DEBUGGER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int rockchip_debug_dump_edpcsr(struct fiq_debugger_output *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long edpcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int i = 0, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void *pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void *prev_pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 pu = 0, online = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* disable SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) asm volatile("msr daifset, #0x4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) while (rockchip_cpu_debug[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) online = cpu_online(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) output->printf(output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "CPU%d online:%d\n", i, online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (online == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) base = rockchip_cpu_debug[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (pu != EDPRSR_PU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) output->printf(output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "CPU%d power down\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel(EDLAR_UNLOCK, base + EDLAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Try to read a bunch of times if CPU is actually running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) for (j = 0; j < NUM_CPU_SAMPLES &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) printed < NUM_SAMPLES_TO_PRINT; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (pu != EDPRSR_PU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) output->printf(output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "CPU%d power down\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (sizeof(edpcsr) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) edpcsr = ((u64)readl(base + EDPCSR_LO)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ((u64)readl(base + EDPCSR_HI) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) edpcsr = (u32)readl(base + EDPCSR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pc = (void *)(edpcsr & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (pc != prev_pc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) output->printf(output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "\tPC: <0x%px> %pS\n", pc, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) printed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) prev_pc = pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) output->printf(output, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) prev_pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* enable SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) asm volatile("msr daifclr, #0x4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int rockchip_debug_dump_pmpcsr(struct fiq_debugger_output *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u64 pmpcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int i = 0, j = 0, el, ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void *pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void *prev_pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 pu = 0, online = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* disable SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) asm volatile("msr daifset, #0x4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) while (rockchip_cs_pmu[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) online = cpu_online(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) output->printf(output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "CPU%d online:%d\n", i, online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (online == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (pu != EDPRSR_PU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) output->printf(output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "CPU%d power down\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) base = rockchip_cs_pmu[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Try to read a bunch of times if CPU is actually running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) for (j = 0; j < NUM_CPU_SAMPLES &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) printed < NUM_SAMPLES_TO_PRINT; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (pu != EDPRSR_PU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) output->printf(output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "CPU%d power down\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pmpcsr = ((u64)readl(base + PMPCSR_LO)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ((u64)readl(base + PMPCSR_HI) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) el = (pmpcsr >> 61) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (pmpcsr & 0x8000000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ns = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (el == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) pmpcsr |= 0xff00000000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pmpcsr &= 0x0fffffffffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pc = (void *)(pmpcsr & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (pc != prev_pc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) output->printf(output, "\tEL%d(%s) PC: <0x%px> %pS\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) el, ns?"NS":"S", pc, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) printed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) prev_pc = pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) output->printf(output, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) prev_pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* enable SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) asm volatile("msr daifclr, #0x4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int rockchip_debug_dump_pmpcsr(struct fiq_debugger_output *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int rockchip_debug_dump_pcsr(struct fiq_debugger_output *output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (edpcsr_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rockchip_debug_dump_edpcsr(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) rockchip_debug_dump_pmpcsr(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) EXPORT_SYMBOL_GPL(rockchip_debug_dump_pcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int rockchip_panic_notify_edpcsr(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned long event, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long edpcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int i = 0, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) void *pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void *prev_pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 pu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* disable SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) asm volatile("msr daifset, #0x4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * The panic handler will try to shut down the other CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * If any of them are still online at this point, this loop attempts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * to determine the program counter value. If there are no wedged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * CPUs, this loop will do nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) while (rockchip_cpu_debug[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) base = rockchip_cpu_debug[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (pu != EDPRSR_PU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pr_err("CPU%d power down\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Unlock EDLSR.SLK so that EDPCSRhi gets populated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) writel(EDLAR_UNLOCK, base + EDLAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pr_err("CPU%d online:%d\n", i, cpu_online(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Try to read a bunch of times if CPU is actually running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) for (j = 0; j < NUM_CPU_SAMPLES &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) printed < NUM_SAMPLES_TO_PRINT; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pu = (u32)readl(base + EDPRSR) & EDPRSR_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (pu != EDPRSR_PU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pr_err("CPU%d power down\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (sizeof(edpcsr) == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) edpcsr = ((u64)readl(base + EDPCSR_LO)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ((u64)readl(base + EDPCSR_HI) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) edpcsr = (u32)readl(base + EDPCSR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pc = (void *)(edpcsr & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (pc != prev_pc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pr_err("\tPC: <0x%px> %pS\n", pc, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) printed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) prev_pc = pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pr_err("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) prev_pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* enable SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) asm volatile("msr daifclr, #0x4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #ifdef CONFIG_ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int rockchip_panic_notify_pmpcsr(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) unsigned long event, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u64 pmpcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int i = 0, j, el, ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) void *pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void *prev_pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 pu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* disable SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) asm volatile("msr daifset, #0x4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * The panic handler will try to shut down the other CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * If any of them are still online at this point, this loop attempts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * to determine the program counter value. If there are no wedged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * CPUs, this loop will do nothing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) while (rockchip_cs_pmu[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) base = rockchip_cs_pmu[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pr_err("CPU%d online:%d\n", i, cpu_online(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (pu != EDPRSR_PU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pr_err("CPU%d power down\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Try to read a bunch of times if CPU is actually running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) for (j = 0; j < NUM_CPU_SAMPLES &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) printed < NUM_SAMPLES_TO_PRINT; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) pu = (u32)readl(rockchip_cpu_debug[i] + EDPRSR) & EDPRSR_PU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (pu != EDPRSR_PU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pr_err("CPU%d power down\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pmpcsr = ((u64)readl(base + PMPCSR_LO)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ((u64)readl(base + PMPCSR_HI) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) el = (pmpcsr >> 61) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (pmpcsr & 0x8000000000000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ns = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ns = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (el == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pmpcsr |= 0xff00000000000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pmpcsr &= 0x0fffffffffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* NOTE: no offset on ARMv8; see DBGDEVID1.PCSROffset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) pc = (void *)(pmpcsr & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (pc != prev_pc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pr_err("\tEL%d(%s) PC: <0x%px> %pS\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) el, ns?"NS":"S", pc, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) printed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) prev_pc = pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) pr_err("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) prev_pc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) printed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* enable SError */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) asm volatile("msr daifclr, #0x4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int rockchip_panic_notify_pmpcsr(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned long event, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int rockchip_show_interrupts(char *p, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int prec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) char *buf = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned long any_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int i = irq, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct irqaction *action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct irq_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (i > nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* print header and calculate the width of the first column */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) j *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) buf += sprintf(buf, "%*s", prec + 8, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) for_each_online_cpu(j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) buf += sprintf(buf, "CPU%-8d", j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) buf += sprintf(buf, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) desc = irq_to_desc(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (!desc || (desc->status_use_accessors & IRQ_HIDDEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) goto outsparse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (desc->kstat_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for_each_online_cpu(j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) any_count |= *per_cpu_ptr(desc->kstat_irqs, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if ((!desc->action) && !any_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto outsparse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) buf += sprintf(buf, "%*d: ", prec, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for_each_online_cpu(j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) buf += sprintf(buf, "%10u ", desc->kstat_irqs ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *per_cpu_ptr(desc->kstat_irqs, j) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (desc->irq_data.chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (desc->irq_data.chip->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) buf += sprintf(buf, " %8s", desc->irq_data.chip->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) buf += sprintf(buf, " %8s", "-");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) buf += sprintf(buf, " %8s", "None");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (desc->irq_data.domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) buf += sprintf(buf, " %*lu", prec, desc->irq_data.hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) buf += sprintf(buf, " %*s", prec, "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #ifdef CONFIG_GENERIC_IRQ_SHOW_LEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) buf += sprintf(buf, " %-8s", irqd_is_level_type(&desc->irq_data) ? "Level" : "Edge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (desc->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) buf += sprintf(buf, "-%-8s", desc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) action = desc->action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (action) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) buf += sprintf(buf, " %s", action->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) while ((action = action->next) != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) buf += sprintf(buf, ", %s", action->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) sprintf(buf, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) outsparse:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static void rockchip_panic_notify_dump_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) for (i = 0; i < nr_irqs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!rockchip_show_interrupts(log_buf, i) || i == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) printk("%s", log_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int rockchip_panic_notify(struct notifier_block *nb, unsigned long event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (edpcsr_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) rockchip_panic_notify_edpcsr(nb, event, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) rockchip_panic_notify_pmpcsr(nb, event, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) rockchip_panic_notify_dump_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) rockchip_panic_notify_dump_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static struct notifier_block rockchip_panic_nb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .notifier_call = rockchip_panic_notify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const struct of_device_id rockchip_debug_dt_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* external debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .compatible = "rockchip,debug",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct of_device_id rockchip_cspmu_dt_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* coresight pmu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .compatible = "rockchip,cspmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int __init rockchip_debug_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 pcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct device_node *debug_np = NULL, *cspmu_np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) debug_np = of_find_matching_node_and_match(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) rockchip_debug_dt_match, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (debug_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) i = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) rockchip_cpu_debug[i] = of_iomap(debug_np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } while (rockchip_cpu_debug[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) of_node_put(debug_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cspmu_np = of_find_matching_node_and_match(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) rockchip_cspmu_dt_match, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (cspmu_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) i = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) rockchip_cs_pmu[i] = of_iomap(cspmu_np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) } while (rockchip_cs_pmu[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) of_node_put(cspmu_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!debug_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pcs = readl(rockchip_cpu_debug[0] + EDDEVID) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* 0x3 EDPCSR, EDCIDSR, and EDVIDSR are implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (pcs == 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) edpcsr_present = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!edpcsr_present && !cspmu_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) atomic_notifier_chain_register(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) &rockchip_panic_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (IS_ENABLED(CONFIG_NO_GKI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) atomic_notifier_chain_register(&hardlock_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) &rockchip_panic_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) atomic_notifier_chain_register(&rcu_stall_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) &rockchip_panic_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) arch_initcall(rockchip_debug_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void __exit rockchip_debug_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) atomic_notifier_chain_unregister(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) &rockchip_panic_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (IS_ENABLED(CONFIG_NO_GKI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (IS_ENABLED(CONFIG_HARDLOCKUP_DETECTOR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) atomic_notifier_chain_unregister(&hardlock_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) &rockchip_panic_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) atomic_notifier_chain_unregister(&rcu_stall_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) &rockchip_panic_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) while (rockchip_cpu_debug[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) iounmap(rockchip_cpu_debug[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) while (rockchip_cs_pmu[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) iounmap(rockchip_cs_pmu[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) module_exit(rockchip_debug_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MODULE_AUTHOR("Huibin Hong <huibin.hong@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MODULE_DESCRIPTION("Rockchip Debugger");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MODULE_ALIAS("platform:rockchip-debugger");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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