Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2017 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This program is free software; you can redistribute it and/or modify it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * under the terms of version 2 of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This program is distributed in the hope that it will be useful, but WITHOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/system_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) unsigned long rockchip_soc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) EXPORT_SYMBOL(rockchip_soc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static int rockchip_cpuinfo_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct nvmem_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned char *efuse_buf, buf[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	cell = nvmem_cell_get(dev, "cpu-code");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	if (!IS_ERR(cell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		efuse_buf = nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		if (IS_ERR(efuse_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 			return PTR_ERR(efuse_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		if (len == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			rockchip_set_cpu((efuse_buf[0] << 8 | efuse_buf[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		kfree(efuse_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	cell = nvmem_cell_get(dev, "cpu-version");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (!IS_ERR(cell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		efuse_buf = nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		if (IS_ERR(efuse_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			return PTR_ERR(efuse_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		if ((len == 1) && (efuse_buf[0] > rockchip_get_cpu_version()))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 			rockchip_set_cpu_version(efuse_buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		kfree(efuse_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	cell = nvmem_cell_get(dev, "id");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (IS_ERR(cell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		dev_err(dev, "failed to get id cell: %ld\n", PTR_ERR(cell));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		if (PTR_ERR(cell) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 			return PTR_ERR(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return PTR_ERR(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	efuse_buf = nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (IS_ERR(efuse_buf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return PTR_ERR(efuse_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (len != 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		kfree(efuse_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		dev_err(dev, "invalid id len: %zu\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		buf[i] = efuse_buf[1 + (i << 1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		buf[i + 8] = efuse_buf[i << 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	kfree(efuse_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	dev_info(dev, "SoC\t\t: %lx\n", rockchip_soc_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #ifdef CONFIG_NO_GKI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	system_serial_low = crc32(0, buf, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	system_serial_high = crc32(system_serial_low, buf + 8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	dev_info(dev, "Serial\t\t: %08x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		 system_serial_high, system_serial_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static const struct of_device_id rockchip_cpuinfo_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{ .compatible = "rockchip,cpuinfo", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_DEVICE_TABLE(of, rockchip_cpuinfo_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct platform_driver rockchip_cpuinfo_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.probe = rockchip_cpuinfo_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.name = "rockchip-cpuinfo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.of_match_table = rockchip_cpuinfo_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void rockchip_set_cpu_version_from_os_reg(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	void __iomem *r = ioremap(reg, 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		rockchip_set_cpu_version(readl_relaxed(r) & GENMASK(2, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		iounmap(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void px30_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	rockchip_soc_id = ROCKCHIP_SOC_PX30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PX30_DDR_GRF_BASE	0xFF630000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PX30_DDR_GRF_CON1	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	base = ioremap(PX30_DDR_GRF_BASE, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		unsigned int val = readl_relaxed(base + PX30_DDR_GRF_CON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		if (((val >> 14) & 0x03) == 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			rockchip_soc_id = ROCKCHIP_SOC_PX30S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RV1106_OS_REG1	0xff020204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void rv1103_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	rockchip_soc_id = ROCKCHIP_SOC_RV1103;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	rockchip_set_cpu_version_from_os_reg(RV1106_OS_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void rv1106_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	rockchip_soc_id = ROCKCHIP_SOC_RV1106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	rockchip_set_cpu_version_from_os_reg(RV1106_OS_REG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void rv1109_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	rockchip_soc_id = ROCKCHIP_SOC_RV1109;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void rv1126_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	rockchip_soc_id = ROCKCHIP_SOC_RV1126;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void rk3288_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	rockchip_soc_id = ROCKCHIP_SOC_RK3288;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RK3288_HDMI_PHYS	0xFF980000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	base = ioremap(RK3288_HDMI_PHYS, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		/* RK3288W HDMI Revision ID is 0x1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		if (readl_relaxed(base + 4) == 0x1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			rockchip_soc_id = ROCKCHIP_SOC_RK3288W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void rk3126_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	rockchip_soc_id = ROCKCHIP_SOC_RK3126;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RK312X_GRF_PHYS		0x20008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RK312X_GRF_SOC_CON1	0x00000144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define RK312X_GRF_CHIP_TAG	0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	base = ioremap(RK312X_GRF_PHYS, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (readl_relaxed(base + RK312X_GRF_CHIP_TAG) == 0x3136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			if (readl_relaxed(base + RK312X_GRF_SOC_CON1) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				rockchip_soc_id = ROCKCHIP_SOC_RK3126C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				rockchip_soc_id = ROCKCHIP_SOC_RK3126B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void rk3308_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	rockchip_soc_id = ROCKCHIP_SOC_RK3308;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RK3308_GRF_PHYS		0xFF000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RK3308_GRF_CHIP_ID	0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	base = ioremap(RK3308_GRF_PHYS, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		u32 v = readl_relaxed(base + RK3308_GRF_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (v == 0x3308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			rockchip_soc_id = ROCKCHIP_SOC_RK3308B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		if (v == 0x3308c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			rockchip_soc_id = ROCKCHIP_SOC_RK3308BS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RK356X_PMU_GRF_PHYS		0xfdc20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RK356X_PMU_GRF_SOC_CON0		0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RK356X_CHIP_VERSION_MASK	0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void rk356x_set_cpu_version(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	base = ioremap(RK356X_PMU_GRF_PHYS, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		if (readl_relaxed(base + RK356X_PMU_GRF_SOC_CON0) & RK356X_CHIP_VERSION_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			rockchip_set_cpu_version(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void rk3566_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	rockchip_soc_id = ROCKCHIP_SOC_RK3566;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	rk356x_set_cpu_version();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void rk3568_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	rockchip_soc_id = ROCKCHIP_SOC_RK3568;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	rk356x_set_cpu_version();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int __init rockchip_soc_id_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (rockchip_soc_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (cpu_is_rk3288()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		rk3288_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	} else if (cpu_is_rk312x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		if (of_machine_is_compatible("rockchip,rk3128"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			rockchip_soc_id = ROCKCHIP_SOC_RK3128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			rk3126_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	} else if (cpu_is_rk3308()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		rk3308_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	} else if (cpu_is_rv1103()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		rv1103_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	} else if (cpu_is_rv1106()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		rv1106_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	} else if (cpu_is_rv1109()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		rv1109_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	} else if (cpu_is_rv1126()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		rv1126_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	} else if (cpu_is_rk3566()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		rk3566_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	} else if (cpu_is_rk3568()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		rk3568_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	} else if (cpu_is_px30()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		px30_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pure_initcall(rockchip_soc_id_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int __init rockchip_cpuinfo_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	rockchip_soc_id_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	return platform_driver_register(&rockchip_cpuinfo_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) subsys_initcall_sync(rockchip_cpuinfo_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void __exit rockchip_cpuinfo_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	platform_driver_unregister(&rockchip_cpuinfo_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) module_exit(rockchip_cpuinfo_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MODULE_LICENSE("GPL");