^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Rockchip IO Voltage Domain driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2014 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "../../regulator/internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_SUPPLIES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * The max voltage for 1.8V and 3.3V come from the Rockchip datasheet under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * "Recommended Operating Conditions" for "Digital GPIO". When the typical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * is 3.3V the max is 3.6V. When the typical is 1.8V the max is 1.98V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * They are used like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * - If the voltage on a rail is above the "1.8" voltage (1.98V) we'll tell the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * SoC we're at 3.3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * - If the voltage on a rail is above the "3.3" voltage (3.6V) we'll consider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * that to be an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MAX_VOLTAGE_1_8 1980000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MAX_VOLTAGE_3_3 3600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PX30_IO_VSEL 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PX30_IO_VSEL_VCCIO6_SRC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PX30_IO_VSEL_VCCIO6_SUPPLY_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RK3288_SOC_CON2 0x24c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RK3288_SOC_CON2_FLASH0 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RK3288_SOC_FLASH_SUPPLY_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RK3308_SOC_CON0 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RK3308_SOC_CON0_VCCIO3 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RK3308_SOC_VCCIO3_SUPPLY_NUM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RK3328_SOC_CON4 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RK3328_SOC_CON4_VCCIO2 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RK3328_SOC_VCCIO2_SUPPLY_NUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RK3368_SOC_CON15 0x43c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RK3368_SOC_CON15_FLASH0 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RK3368_SOC_FLASH_SUPPLY_NUM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RK3399_PMUGRF_CON0 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RK3399_PMUGRF_CON0_VSEL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RK3399_PMUGRF_VSEL_SUPPLY_NUM 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RK3568_PMU_GRF_IO_VSEL0 (0x0140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RK3568_PMU_GRF_IO_VSEL1 (0x0144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define RK3568_PMU_GRF_IO_VSEL2 (0x0148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct rockchip_iodomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @supplies: voltage settings matching the register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct rockchip_iodomain_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int grf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const char *supply_names[MAX_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) void (*init)(struct rockchip_iodomain *iod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct rockchip_iodomain_supply {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct rockchip_iodomain *iod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct notifier_block nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct rockchip_iodomain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const struct rockchip_iodomain_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct rockchip_iodomain_supply supplies[MAX_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int (*write)(struct rockchip_iodomain_supply *supply, int uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int rk3568_pmu_iodomain_write(struct rockchip_iodomain_supply *supply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct rockchip_iodomain *iod = supply->iod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 is_3v3 = uV > MAX_VOLTAGE_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 val0, val1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) switch (supply->idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case 0: /* pmuio1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case 1: /* pmuio2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) b = supply->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) b = supply->idx + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL2, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case 3: /* vccio2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case 2: /* vccio1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case 4: /* vccio3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case 5: /* vccio4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case 6: /* vccio5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case 7: /* vccio6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case 8: /* vccio7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) b = supply->idx - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL0, val0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) regmap_write(iod->grf, RK3568_PMU_GRF_IO_VSEL1, val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int rockchip_iodomain_write(struct rockchip_iodomain_supply *supply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct rockchip_iodomain *iod = supply->iod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* set value bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val = (uV > MAX_VOLTAGE_1_8) ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) val <<= supply->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* apply hiword-mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val |= (BIT(supply->idx) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ret = regmap_write(iod->grf, iod->soc_data->grf_offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(iod->dev, "Couldn't write to GRF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int rockchip_iodomain_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct rockchip_iodomain_supply *supply =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) container_of(nb, struct rockchip_iodomain_supply, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * According to Rockchip it's important to keep the SoC IO domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * higher than (or equal to) the external voltage. That means we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * to change it before external voltage changes happen in the case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * of an increase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Note that in the "pre" change we pick the max possible voltage that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * the regulator might end up at (the client requests a range and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * don't know for certain the exact voltage). Right now we rely on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * slop in MAX_VOLTAGE_1_8 and MAX_VOLTAGE_3_3 to save us if clients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * request something like a max of 3.6V when they really want 3.3V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * We could attempt to come up with better rules if this fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (event & REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct pre_voltage_change_data *pvc_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) uV = max_t(unsigned long, pvc_data->old_uV, pvc_data->max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else if (event & (REGULATOR_EVENT_VOLTAGE_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) uV = (unsigned long)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_dbg(supply->iod->dev, "Setting to %d\n", uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (uV > MAX_VOLTAGE_3_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(supply->iod->dev, "Voltage too high: %d\n", uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ret = supply->iod->write(supply, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret && event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_dbg(supply->iod->dev, "Setting to %d done\n", uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void px30_iodomain_init(struct rockchip_iodomain *iod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* if no VCCIO6 supply we should leave things alone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!iod->supplies[PX30_IO_VSEL_VCCIO6_SUPPLY_NUM].reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * set vccio6 iodomain to also use this framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * instead of a special gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) val = PX30_IO_VSEL_VCCIO6_SRC | (PX30_IO_VSEL_VCCIO6_SRC << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = regmap_write(iod->grf, PX30_IO_VSEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_warn(iod->dev, "couldn't update vccio6 ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void rk3288_iodomain_init(struct rockchip_iodomain *iod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* if no flash supply we should leave things alone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (!iod->supplies[RK3288_SOC_FLASH_SUPPLY_NUM].reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * set flash0 iodomain to also use this framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * instead of a special gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) val = RK3288_SOC_CON2_FLASH0 | (RK3288_SOC_CON2_FLASH0 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = regmap_write(iod->grf, RK3288_SOC_CON2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void rk3308_iodomain_init(struct rockchip_iodomain *iod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* if no vccio3 supply we should leave things alone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!iod->supplies[RK3308_SOC_VCCIO3_SUPPLY_NUM].reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * set vccio3 iodomain to also use this framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * instead of a special gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) val = RK3308_SOC_CON0_VCCIO3 | (RK3308_SOC_CON0_VCCIO3 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = regmap_write(iod->grf, RK3308_SOC_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_warn(iod->dev, "couldn't update vccio3 vsel ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void rk3328_iodomain_init(struct rockchip_iodomain *iod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* if no vccio2 supply we should leave things alone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (!iod->supplies[RK3328_SOC_VCCIO2_SUPPLY_NUM].reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * set vccio2 iodomain to also use this framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * instead of a special gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val = RK3328_SOC_CON4_VCCIO2 | (RK3328_SOC_CON4_VCCIO2 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = regmap_write(iod->grf, RK3328_SOC_CON4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_warn(iod->dev, "couldn't update vccio2 vsel ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void rk3368_iodomain_init(struct rockchip_iodomain *iod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* if no flash supply we should leave things alone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (!iod->supplies[RK3368_SOC_FLASH_SUPPLY_NUM].reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * set flash0 iodomain to also use this framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * instead of a special gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) val = RK3368_SOC_CON15_FLASH0 | (RK3368_SOC_CON15_FLASH0 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = regmap_write(iod->grf, RK3368_SOC_CON15, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_warn(iod->dev, "couldn't update flash0 ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void rk3399_pmu_iodomain_init(struct rockchip_iodomain *iod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* if no pmu io supply we should leave things alone */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!iod->supplies[RK3399_PMUGRF_VSEL_SUPPLY_NUM].reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * set pmu io iodomain to also use this framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * instead of a special gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) val = RK3399_PMUGRF_CON0_VSEL | (RK3399_PMUGRF_CON0_VSEL << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = regmap_write(iod->grf, RK3399_PMUGRF_CON0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_warn(iod->dev, "couldn't update pmu io iodomain ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct rockchip_iodomain_soc_data soc_data_px30 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .grf_offset = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "vccio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "vccio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "vccio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "vccio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "vccio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "vccio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "vccio-oscgpi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .init = px30_iodomain_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct rockchip_iodomain_soc_data soc_data_px30_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .grf_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "pmuio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "pmuio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * On the rk3188 the io-domains are handled by a shared register with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * lower 8 bits being still being continuing drive-strength settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct rockchip_iodomain_soc_data soc_data_rk3188 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .grf_offset = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "ap0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "ap1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "cif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "vccio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "vccio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "lcdc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "lcdc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct rockchip_iodomain_soc_data soc_data_rk3228 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .grf_offset = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "vccio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) "vccio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "vccio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "vccio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct rockchip_iodomain_soc_data soc_data_rk3288 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .grf_offset = 0x380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "lcdc", /* LCDC_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) "dvp", /* DVPIO_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "flash0", /* FLASH0_VDD (emmc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "flash1", /* FLASH1_VDD (sdio1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "wifi", /* APIO3_VDD (sdio0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "bb", /* APIO5_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "audio", /* APIO4_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "sdcard", /* SDMMC0_VDD (sdmmc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "gpio30", /* APIO1_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "gpio1830", /* APIO2_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .init = rk3288_iodomain_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct rockchip_iodomain_soc_data soc_data_rk3308 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .grf_offset = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "vccio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) "vccio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "vccio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) "vccio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "vccio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) "vccio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .init = rk3308_iodomain_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct rockchip_iodomain_soc_data soc_data_rk3328 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .grf_offset = 0x410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "vccio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "vccio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) "vccio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "vccio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "vccio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "vccio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) "pmuio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .init = rk3328_iodomain_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const struct rockchip_iodomain_soc_data soc_data_rk3368 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .grf_offset = 0x900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) NULL, /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "dvp", /* DVPIO_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "flash0", /* FLASH0_VDD (emmc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "wifi", /* APIO2_VDD (sdio0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "audio", /* APIO3_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "sdcard", /* SDMMC0_VDD (sdmmc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "gpio30", /* APIO1_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "gpio1830", /* APIO4_VDD (gpujtag) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .init = rk3368_iodomain_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct rockchip_iodomain_soc_data soc_data_rk3368_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .grf_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "pmu", /*PMU IO domain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "vop", /*LCDC IO domain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const struct rockchip_iodomain_soc_data soc_data_rk3399 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .grf_offset = 0xe640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "bt656", /* APIO2_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "audio", /* APIO5_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "sdmmc", /* SDMMC0_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "gpio1830", /* APIO4_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct rockchip_iodomain_soc_data soc_data_rk3399_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .grf_offset = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "pmu1830", /* PMUIO2_VDD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .init = rk3399_pmu_iodomain_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct rockchip_iodomain_soc_data soc_data_rk3568_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .grf_offset = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "pmuio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) "pmuio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) "vccio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "vccio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "vccio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "vccio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "vccio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "vccio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "vccio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const struct rockchip_iodomain_soc_data soc_data_rv1108 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .grf_offset = 0x404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "vccio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "vccio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "vccio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) "vccio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "vccio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct rockchip_iodomain_soc_data soc_data_rv1108_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .grf_offset = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) "pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct rockchip_iodomain_soc_data soc_data_rv1126_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .grf_offset = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .supply_names = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "vccio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) "vccio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "vccio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "vccio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "vccio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "vccio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "vccio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) "pmuio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "pmuio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const struct of_device_id rockchip_iodomain_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #ifdef CONFIG_CPU_PX30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .compatible = "rockchip,px30-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .data = (void *)&soc_data_px30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .compatible = "rockchip,px30-pmu-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .data = (void *)&soc_data_px30_pmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #ifdef CONFIG_CPU_RK3188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .compatible = "rockchip,rk3188-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .data = &soc_data_rk3188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #ifdef CONFIG_CPU_RK322X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .compatible = "rockchip,rk3228-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .data = &soc_data_rk3228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #ifdef CONFIG_CPU_RK3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .compatible = "rockchip,rk3288-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .data = &soc_data_rk3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #ifdef CONFIG_CPU_RK3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .compatible = "rockchip,rk3308-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .data = &soc_data_rk3308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #ifdef CONFIG_CPU_RK3328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .compatible = "rockchip,rk3328-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .data = &soc_data_rk3328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #ifdef CONFIG_CPU_RK3368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .compatible = "rockchip,rk3368-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .data = &soc_data_rk3368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .compatible = "rockchip,rk3368-pmu-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .data = &soc_data_rk3368_pmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #ifdef CONFIG_CPU_RK3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .compatible = "rockchip,rk3399-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .data = &soc_data_rk3399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .compatible = "rockchip,rk3399-pmu-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .data = &soc_data_rk3399_pmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #ifdef CONFIG_CPU_RK3568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .compatible = "rockchip,rk3568-pmu-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .data = &soc_data_rk3568_pmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #ifdef CONFIG_CPU_RV1108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .compatible = "rockchip,rv1108-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .data = &soc_data_rv1108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .compatible = "rockchip,rv1108-pmu-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .data = &soc_data_rv1108_pmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #ifdef CONFIG_CPU_RV1126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .compatible = "rockchip,rv1126-pmu-io-voltage-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .data = &soc_data_rv1126_pmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MODULE_DEVICE_TABLE(of, rockchip_iodomain_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #ifndef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const char *rdev_get_name(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (rdev->constraints && rdev->constraints->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return rdev->constraints->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else if (rdev->desc->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return rdev->desc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct device_node *of_get_child_regulator(struct device_node *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) const char *prop_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct device_node *regnode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct device_node *child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) for_each_child_of_node(parent, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) regnode = of_parse_phandle(child, prop_name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!regnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) regnode = of_get_child_regulator(child, prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (regnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return regnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return regnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static struct device_node *of_get_regulator(struct device *dev, const char *supply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct device_node *regnode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) char prop_name[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_dbg(dev, "Looking up %s-supply from device tree\n", supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) snprintf(prop_name, sizeof(prop_name), "%s-supply", supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) regnode = of_parse_phandle(dev->of_node, prop_name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!regnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) regnode = of_get_child_regulator(dev->of_node, prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (regnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return regnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_dbg(dev, "Looking up %s property in node %pOF failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) prop_name, dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return regnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static void rockchip_iodomain_dump(const struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct rockchip_iodomain_supply *supply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct rockchip_iodomain *iod = supply->iod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) const char *name = iod->soc_data->supply_names[supply->idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct device *dev = iod->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct regulator_dev *r = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) node = of_get_regulator(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) r = of_find_regulator_by_node(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!IS_ERR_OR_NULL(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_info(&pdev->dev, "%s(%d uV) supplied by %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) name, regulator_get_voltage(supply->reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) rdev_get_name(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) rockchip_iodomain_dump(const struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct rockchip_iodomain_supply *supply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int rv1126_iodomain_notify(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned long event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct rockchip_iodomain_supply *supply =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) container_of(nb, struct rockchip_iodomain_supply, nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (event & REGULATOR_EVENT_PRE_VOLTAGE_CHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct pre_voltage_change_data *pvc_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) uV = max_t(unsigned long, pvc_data->old_uV, pvc_data->max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } else if (event & (REGULATOR_EVENT_VOLTAGE_CHANGE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) REGULATOR_EVENT_ABORT_VOLTAGE_CHANGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) uV = (unsigned long)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) } else if (event & REGULATOR_EVENT_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) uV = MAX_VOLTAGE_3_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) } else if (event & REGULATOR_EVENT_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) uV = (unsigned long)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (uV <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_err(supply->iod->dev, "Voltage invalid: %d\n", uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) dev_dbg(supply->iod->dev, "Setting to %d\n", uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (uV > MAX_VOLTAGE_3_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(supply->iod->dev, "Voltage too high: %d\n", uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = supply->iod->write(supply, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (ret && event == REGULATOR_EVENT_PRE_VOLTAGE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_dbg(supply->iod->dev, "Setting to %d done\n", uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int rockchip_iodomain_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct rockchip_iodomain *iod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) iod = devm_kzalloc(&pdev->dev, sizeof(*iod), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (!iod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) iod->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) platform_set_drvdata(pdev, iod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) match = of_match_node(rockchip_iodomain_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) iod->soc_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (IS_ENABLED(CONFIG_CPU_RK3568) && match->data == &soc_data_rk3568_pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) iod->write = rk3568_pmu_iodomain_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) iod->write = rockchip_iodomain_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (parent && parent->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) iod->grf = syscon_node_to_regmap(parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_dbg(&pdev->dev, "falling back to old binding\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) iod->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (IS_ERR(iod->grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_err(&pdev->dev, "couldn't find grf regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return PTR_ERR(iod->grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) for (i = 0; i < MAX_SUPPLIES; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) const char *supply_name = iod->soc_data->supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct rockchip_iodomain_supply *supply = &iod->supplies[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct regulator *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (!supply_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* PX30s pmuio1 not support 1v8 mode switch. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (soc_is_px30s() && (!strcmp(supply_name, "pmuio1")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) reg = devm_regulator_get_optional(iod->dev, supply_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (IS_ERR(reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* If a supply wasn't specified, that's OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) else if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_err(iod->dev, "couldn't get regulator %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) supply_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) goto unreg_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* set initial correct value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) uV = regulator_get_voltage(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* must be a regulator we can get the voltage of */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (uV < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(iod->dev, "Can't determine voltage: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) supply_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) goto unreg_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (uV > MAX_VOLTAGE_3_3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_crit(iod->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "%d uV is too high. May damage SoC!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) goto unreg_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* setup our supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) supply->idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) supply->iod = iod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) supply->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) supply->nb.notifier_call = rockchip_iodomain_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (IS_ENABLED(CONFIG_CPU_RV1126))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) supply->nb.notifier_call = rv1126_iodomain_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ret = iod->write(supply, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) supply->reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) goto unreg_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* register regulator notifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret = regulator_register_notifier(reg, &supply->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) "regulator notifier request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) supply->reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) goto unreg_notify;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) rockchip_iodomain_dump(pdev, supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (iod->soc_data->init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) iod->soc_data->init(iod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) unreg_notify:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) for (i = MAX_SUPPLIES - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct rockchip_iodomain_supply *io_supply = &iod->supplies[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (io_supply->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) regulator_unregister_notifier(io_supply->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) &io_supply->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int rockchip_iodomain_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct rockchip_iodomain *iod = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) for (i = MAX_SUPPLIES - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct rockchip_iodomain_supply *io_supply = &iod->supplies[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (io_supply->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) regulator_unregister_notifier(io_supply->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) &io_supply->nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static struct platform_driver rockchip_iodomain_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .probe = rockchip_iodomain_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .remove = rockchip_iodomain_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .name = "rockchip-iodomain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .of_match_table = rockchip_iodomain_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static int __init rockchip_iodomain_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return platform_driver_register(&rockchip_iodomain_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) fs_initcall(rockchip_iodomain_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static void __exit rockchip_iodomain_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) platform_driver_unregister(&rockchip_iodomain_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) module_exit(rockchip_iodomain_driver_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) MODULE_DESCRIPTION("Rockchip IO-domain driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) MODULE_AUTHOR("Doug Anderson <dianders@chromium.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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