Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Rockchip Generic Register Files setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) struct rockchip_grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct rockchip_grf_funcs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	int (*reset)(struct rockchip_grf *grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) struct rockchip_grf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	const struct rockchip_grf_funcs *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static int rockchip_edp_phy_grf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct rockchip_grf *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	grf = devm_kzalloc(dev, sizeof(*grf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	if (!grf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	grf->funcs = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (!grf->funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	grf->regmap = syscon_node_to_regmap(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	if (IS_ERR(grf->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		ret = PTR_ERR(grf->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		dev_err(dev, "failed to get grf: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	ret = grf->funcs->reset(grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	platform_set_drvdata(pdev, grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) static int __maybe_unused rockchip_edp_phy_grf_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct rockchip_grf *grf = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return grf->funcs->reset(grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static const struct dev_pm_ops rockchip_edp_phy_grf_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rockchip_edp_phy_grf_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static int rk3568_edp_phy_grf_reset(struct rockchip_grf *grf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	ret = regmap_read(grf->regmap, 0x0030, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (!FIELD_GET(0x1, status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		regmap_write(grf->regmap, 0x0028, 0x00070007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		regmap_write(grf->regmap, 0x0000, 0x0ff10ff1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static const struct rockchip_grf_funcs rk3568_edp_phy_grf_funcs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.reset = rk3568_edp_phy_grf_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static const struct of_device_id rockchip_edp_phy_grf_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.compatible = "rockchip,rk3568-edp-phy-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.data = &rk3568_edp_phy_grf_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) MODULE_DEVICE_TABLE(of, rockchip_edp_phy_grf_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static struct platform_driver rockchip_edp_phy_grf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.name = "rockchip-edp-phy-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.of_match_table = rockchip_edp_phy_grf_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.pm = &rockchip_edp_phy_grf_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.probe = rockchip_edp_phy_grf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HIWORD_UPDATE(val, mask, shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		((val) << (shift) | (mask) << ((shift) + 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct rockchip_grf_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	const char *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct rockchip_grf_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	const struct rockchip_grf_value *values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	int num_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PX30_GRF_SOC_CON5		0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const struct rockchip_grf_value px30_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 * Postponing auto jtag/sdmmc switching by 5 seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 * The counter value is calculated based on 24MHz clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ "jtag switching delay", PX30_GRF_SOC_CON5, 0x7270E00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct rockchip_grf_info px30_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.values = px30_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.num_values = ARRAY_SIZE(px30_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RK3036_GRF_SOC_CON0		0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct rockchip_grf_value rk3036_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * Disable auto jtag/sdmmc switching that causes issues with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 * clock-framework and the mmc controllers making them unreliable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{ "jtag switching", RK3036_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct rockchip_grf_info rk3036_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.values = rk3036_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.num_values = ARRAY_SIZE(rk3036_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RK3128_GRF_SOC_CON0		0x140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct rockchip_grf_value rk3128_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ "jtag switching", RK3128_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct rockchip_grf_info rk3128_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.values = rk3128_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.num_values = ARRAY_SIZE(rk3128_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RK3228_GRF_SOC_CON6		0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct rockchip_grf_value rk3228_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	{ "jtag switching", RK3228_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct rockchip_grf_info rk3228_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.values = rk3228_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.num_values = ARRAY_SIZE(rk3228_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RK3288_GRF_SOC_CON0		0x244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RK3288_GRF_SOC_CON2		0x24c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct rockchip_grf_value rk3288_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{ "jtag switching", RK3288_GRF_SOC_CON0, HIWORD_UPDATE(0, 1, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ "pwm select", RK3288_GRF_SOC_CON2, HIWORD_UPDATE(1, 1, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct rockchip_grf_info rk3288_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.values = rk3288_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.num_values = ARRAY_SIZE(rk3288_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define RK3328_GRF_SOC_CON4		0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct rockchip_grf_value rk3328_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{ "jtag switching", RK3328_GRF_SOC_CON4, HIWORD_UPDATE(0, 1, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct rockchip_grf_info rk3328_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.values = rk3328_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.num_values = ARRAY_SIZE(rk3328_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RK3308_GRF_SOC_CON3		0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RK3308_GRF_SOC_CON13		0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct rockchip_grf_value rk3308_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ "uart dma mask", RK3308_GRF_SOC_CON3, HIWORD_UPDATE(0, 0x1f, 10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	{ "uart2 auto switching", RK3308_GRF_SOC_CON13, HIWORD_UPDATE(0, 0x1, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct rockchip_grf_info rk3308_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.values = rk3308_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.num_values = ARRAY_SIZE(rk3308_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RK3368_GRF_SOC_CON15		0x43c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const struct rockchip_grf_value rk3368_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	{ "jtag switching", RK3368_GRF_SOC_CON15, HIWORD_UPDATE(0, 1, 13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct rockchip_grf_info rk3368_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.values = rk3368_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.num_values = ARRAY_SIZE(rk3368_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define RK3399_GRF_SOC_CON7		0xe21c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct rockchip_grf_value rk3399_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	{ "jtag switching", RK3399_GRF_SOC_CON7, HIWORD_UPDATE(0, 1, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct rockchip_grf_info rk3399_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.values = rk3399_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.num_values = ARRAY_SIZE(rk3399_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define RK3588_SYS_GRF_SOC_CON7		0x031c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct rockchip_grf_value rk3588_sys_grf_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	{ "Connect EDP hpd to IO", RK3588_SYS_GRF_SOC_CON7, HIWORD_UPDATE(0x3, 0x3, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct rockchip_grf_info rk3588_sys_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.values = rk3588_sys_grf_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.num_values = ARRAY_SIZE(rk3588_sys_grf_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DELAY_ONE_SECOND		0x16E3600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define RV1126_GRF1_SDDETFLT_CON	0x10254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define RV1126_GRF1_UART2RX_LOW_CON	0x10258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define RV1126_GRF1_IOFUNC_CON1		0x10264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define RV1126_GRF1_IOFUNC_CON3		0x1026C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define RV1126_JTAG_GROUP0		0x0      /* mux to sdmmc*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define RV1126_JTAG_GROUP1		0x1      /* mux to uart2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define FORCE_JTAG_ENABLE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define FORCE_JTAG_DISABLE		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct rockchip_grf_value rv1126_defaults[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	{ "jtag group0 force", RV1126_GRF1_IOFUNC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		HIWORD_UPDATE(FORCE_JTAG_DISABLE, 1, 4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	{ "jtag group1 force", RV1126_GRF1_IOFUNC_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		HIWORD_UPDATE(FORCE_JTAG_DISABLE, 1, 5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	{ "jtag group1 tms low delay", RV1126_GRF1_UART2RX_LOW_CON, DELAY_ONE_SECOND },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	{ "switch to jtag groupx", RV1126_GRF1_IOFUNC_CON1, HIWORD_UPDATE(RV1126_JTAG_GROUP0, 1, 15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	{ "jtag group0 switching delay", RV1126_GRF1_SDDETFLT_CON, DELAY_ONE_SECOND * 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const struct rockchip_grf_info rv1126_grf __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.values = rv1126_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.num_values = ARRAY_SIZE(rv1126_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.compatible = "rockchip,px30-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.data = (void *)&px30_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.compatible = "rockchip,rk3036-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.data = (void *)&rk3036_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.compatible = "rockchip,rk3128-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.data = (void *)&rk3128_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.compatible = "rockchip,rk3228-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.data = (void *)&rk3228_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.compatible = "rockchip,rk3288-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.data = (void *)&rk3288_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.compatible = "rockchip,rk3308-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.data = (void *)&rk3308_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.compatible = "rockchip,rk3328-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.data = (void *)&rk3328_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.compatible = "rockchip,rk3368-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.data = (void *)&rk3368_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.compatible = "rockchip,rk3399-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.data = (void *)&rk3399_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.compatible = "rockchip,rk3588-sys-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.data = (void *)&rk3588_sys_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.compatible = "rockchip,rv1126-grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.data = (void *)&rv1126_grf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int __init rockchip_grf_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	const struct rockchip_grf_info *grf_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct regmap *grf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	ret = platform_driver_register(&rockchip_edp_phy_grf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	np = of_find_matching_node_and_match(NULL, rockchip_grf_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 					     &match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (!match || !match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		pr_err("%s: missing grf data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	grf_info = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	grf = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	if (IS_ERR(grf)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		pr_err("%s: could not get grf syscon\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		return PTR_ERR(grf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	for (i = 0; i < grf_info->num_values; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		const struct rockchip_grf_value *val = &grf_info->values[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		pr_debug("%s: adjusting %s in %#6x to %#10x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			val->desc, val->reg, val->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		ret = regmap_write(grf, val->reg, val->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			pr_err("%s: write to %#6x failed with %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			       __func__, val->reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) postcore_initcall(rockchip_grf_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MODULE_DESCRIPTION("Rockchip GRF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_LICENSE("GPL");