^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas R-Car System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __SOC_RENESAS_RCAR_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __SOC_RENESAS_RCAR_SYSC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Power Domain flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PD_CPU BIT(0) /* Area contains main CPU core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PD_CPU_CR PD_CPU /* CPU area has CR (R-Car H1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR (R-Car Gen2/3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Description of a Power Area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct rcar_sysc_area {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u16 chan_offs; /* Offset of PWRSR register for this area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 chan_bit; /* Bit in PWR* (except for PWRUP in PWRSR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 isr_bit; /* Bit in SYSCI*R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int parent; /* -1 if none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int flags; /* See PD_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * SoC-specific Power Area Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct rcar_sysc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int (*init)(void); /* Optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const struct rcar_sysc_area *areas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int num_areas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Optional External Request Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 extmask_offs; /* SYSCEXTMASK register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 extmask_val; /* SYSCEXTMASK register mask value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) extern const struct rcar_sysc_info r8a7742_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) extern const struct rcar_sysc_info r8a7743_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) extern const struct rcar_sysc_info r8a7745_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern const struct rcar_sysc_info r8a77470_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern const struct rcar_sysc_info r8a774a1_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern const struct rcar_sysc_info r8a774b1_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) extern const struct rcar_sysc_info r8a774c0_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) extern const struct rcar_sysc_info r8a774e1_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) extern const struct rcar_sysc_info r8a7779_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) extern const struct rcar_sysc_info r8a7790_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) extern const struct rcar_sysc_info r8a7791_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) extern const struct rcar_sysc_info r8a7792_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern const struct rcar_sysc_info r8a7794_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) extern struct rcar_sysc_info r8a7795_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern const struct rcar_sysc_info r8a77960_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern const struct rcar_sysc_info r8a77961_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern const struct rcar_sysc_info r8a77965_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern const struct rcar_sysc_info r8a77970_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) extern const struct rcar_sysc_info r8a77980_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern const struct rcar_sysc_info r8a77990_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern const struct rcar_sysc_info r8a77995_sysc_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Helpers for fixing up power area tables depending on SoC revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) extern void rcar_sysc_nullify(struct rcar_sysc_area *areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int num_areas, u8 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif /* __SOC_RENESAS_RCAR_SYSC_H__ */