^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R-Car SYSC Power management support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015-2017 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/renesas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/soc/renesas/rcar-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "rcar-sysc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* SYSC Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SYSCSR 0x00 /* SYSC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SYSCISR 0x04 /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SYSCISCR 0x08 /* Interrupt Status Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SYSCIER 0x0c /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SYSCIMR 0x10 /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* SYSC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SYSCSR_PONENB 1 /* Ready for power resume requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Power Control Register Offsets inside the register block for each domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Note: The "CR" registers for ARM cores exist on H1 only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Use PSCI on R-Car Gen3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PWRSR_OFFS 0x00 /* Power Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SYSCSR_RETRIES 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SYSCSR_DELAY_US 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PWRER_RETRIES 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PWRER_DELAY_US 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SYSCISR_RETRIES 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SYSCISR_DELAY_US 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct rcar_sysc_ch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 chan_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 chan_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 isr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void __iomem *rcar_sysc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int sr_bit, reg_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) sr_bit = SYSCSR_PONENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg_offs = PWRONCR_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sr_bit = SYSCSR_POFFENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg_offs = PWROFFCR_OFFS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Wait until SYSC is ready to accept a power request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) for (k = 0; k < SYSCSR_RETRIES; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) udelay(SYSCSR_DELAY_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (k == SYSCSR_RETRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Submit power shutoff or power resume request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) iowrite32(BIT(sysc_ch->chan_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int isr_mask = BIT(sysc_ch->isr_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int chan_mask = BIT(sysc_ch->chan_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spin_lock_irqsave(&rcar_sysc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Mask external power requests for CPU or 3DG domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (rcar_sysc_extmask_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) iowrite32(rcar_sysc_extmask_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) rcar_sysc_base + rcar_sysc_extmask_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * The interrupt source needs to be enabled, but masked, to prevent the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * CPU from receiving it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) rcar_sysc_base + SYSCIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rcar_sysc_base + SYSCIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Submit power shutoff or resume request until it was accepted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) for (k = 0; k < PWRER_RETRIES; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = rcar_sysc_pwr_on_off(sysc_ch, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) status = ioread32(rcar_sysc_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) sysc_ch->chan_offs + PWRER_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (!(status & chan_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) udelay(PWRER_DELAY_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (k == PWRER_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Wait until the power shutoff or resume request has completed * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) for (k = 0; k < SYSCISR_RETRIES; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) udelay(SYSCISR_DELAY_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (k == SYSCISR_RETRIES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (rcar_sysc_extmask_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) iowrite32(0, rcar_sysc_base + rcar_sysc_extmask_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_unlock_irqrestore(&rcar_sysc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (st & BIT(sysc_ch->chan_bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct rcar_sysc_pd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct generic_pm_domain genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct rcar_sysc_ch ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) char name[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return container_of(d, struct rcar_sysc_pd, genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_debug("%s: %s\n", __func__, genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return rcar_sysc_power(&pd->ch, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pr_debug("%s: %s\n", __func__, genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return rcar_sysc_power(&pd->ch, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static bool has_cpg_mstp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct generic_pm_domain *genpd = &pd->genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const char *name = pd->genpd.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (pd->flags & PD_CPU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * This domain contains a CPU core and therefore it should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * only be turned off if the CPU is not in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pr_debug("PM domain %s contains %s\n", name, "CPU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) genpd->flags |= GENPD_FLAG_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) } else if (pd->flags & PD_SCU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * This domain contains an SCU and cache-controller, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * therefore it should only be turned off if the CPU cores are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * not in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pr_debug("PM domain %s contains %s\n", name, "SCU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) genpd->flags |= GENPD_FLAG_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } else if (pd->flags & PD_NO_CR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * This domain cannot be turned off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) genpd->flags |= GENPD_FLAG_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!(pd->flags & (PD_CPU | PD_SCU))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Enable Clock Domain for I/O devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (has_cpg_mstp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) genpd->attach_dev = cpg_mstp_attach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) genpd->detach_dev = cpg_mstp_detach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) genpd->attach_dev = cpg_mssr_attach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) genpd->detach_dev = cpg_mssr_detach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) genpd->power_off = rcar_sysc_pd_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) genpd->power_on = rcar_sysc_pd_power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (pd->flags & (PD_CPU | PD_NO_CR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Skip CPUs (handled by SMP code) and areas without control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pr_debug("%s: Not touching %s\n", __func__, genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto finalize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!rcar_sysc_power_is_off(&pd->ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pr_debug("%s: %s is already powered\n", __func__, genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) goto finalize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rcar_sysc_power(&pd->ch, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) finalize:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) error = pm_genpd_init(genpd, &simple_qos_governor, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pr_err("Failed to init PM domain %s: %d\n", name, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct of_device_id rcar_sysc_matches[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #ifdef CONFIG_SYSC_R8A7742
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #ifdef CONFIG_SYSC_R8A7743
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { .compatible = "renesas,r8a7744-sysc", .data = &r8a7743_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #ifdef CONFIG_SYSC_R8A7745
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #ifdef CONFIG_SYSC_R8A77470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #ifdef CONFIG_SYSC_R8A774A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #ifdef CONFIG_SYSC_R8A774B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #ifdef CONFIG_SYSC_R8A774C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #ifdef CONFIG_SYSC_R8A774E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #ifdef CONFIG_SYSC_R8A7779
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #ifdef CONFIG_SYSC_R8A7790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #ifdef CONFIG_SYSC_R8A7791
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #ifdef CONFIG_SYSC_R8A7792
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #ifdef CONFIG_SYSC_R8A7794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #ifdef CONFIG_SYSC_R8A7795
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #ifdef CONFIG_SYSC_R8A77960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #ifdef CONFIG_SYSC_R8A77961
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #ifdef CONFIG_SYSC_R8A77965
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #ifdef CONFIG_SYSC_R8A77970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #ifdef CONFIG_SYSC_R8A77980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #ifdef CONFIG_SYSC_R8A77990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #ifdef CONFIG_SYSC_R8A77995
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct rcar_pm_domains {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct genpd_onecell_data onecell_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct genpd_onecell_data *rcar_sysc_onecell_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int __init rcar_sysc_pd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) const struct rcar_sysc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct rcar_pm_domains *domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) info = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (info->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) error = info->init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) has_cpg_mstp = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "renesas,cpg-mstp-clocks");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pr_warn("%pOF: Cannot map regs\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) rcar_sysc_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Optional External Request Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) rcar_sysc_extmask_offs = info->extmask_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) rcar_sysc_extmask_val = info->extmask_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) domains = kzalloc(sizeof(*domains), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!domains) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) domains->onecell_data.domains = domains->domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) rcar_sysc_onecell_data = &domains->onecell_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) for (i = 0; i < info->num_areas; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) const struct rcar_sysc_area *area = &info->areas[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct rcar_sysc_pd *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!area->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Skip NULLified area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) strcpy(pd->name, area->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pd->genpd.name = pd->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pd->ch.chan_offs = area->chan_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pd->ch.chan_bit = area->chan_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pd->ch.isr_bit = area->isr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pd->flags = area->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) error = rcar_sysc_pd_setup(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) domains->domains[area->isr_bit] = &pd->genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (area->parent < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) error = pm_genpd_add_subdomain(domains->domains[area->parent],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) &pd->genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pr_warn("Failed to add PM subdomain %s to parent %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) area->name, area->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) out_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) early_initcall(rcar_sysc_pd_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void __init rcar_sysc_nullify(struct rcar_sysc_area *areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int num_areas, u8 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (i = 0; i < num_areas; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (areas[i].isr_bit == id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) areas[i].name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #ifdef CONFIG_ARCH_R8A7779
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int rcar_sysc_power_cpu(unsigned int idx, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct generic_pm_domain *genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct rcar_sysc_pd *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (!rcar_sysc_onecell_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) for (i = 0; i < rcar_sysc_onecell_data->num_domains; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) genpd = rcar_sysc_onecell_data->domains[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (!genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) pd = to_rcar_pd(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return rcar_sysc_power(&pd->ch, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int rcar_sysc_power_down_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return rcar_sysc_power_cpu(cpu, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int rcar_sysc_power_up_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return rcar_sysc_power_cpu(cpu, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #endif /* CONFIG_ARCH_R8A7779 */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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