^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas R-Car V3U System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/renesas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <dt-bindings/power/r8a779a0-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Power Domain flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PD_CPU BIT(0) /* Area contains main CPU core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PD_SCU BIT(1) /* Area contains SCU and L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PD_NO_CR BIT(2) /* Area lacks PWR{ON,OFF}CR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PD_CPU_NOCR PD_CPU | PD_NO_CR /* CPU area lacks CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PD_ALWAYS_ON PD_NO_CR /* Always-on area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Description of a Power Area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct r8a779a0_sysc_area {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 pdr; /* PDRn */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int parent; /* -1 if none */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned int flags; /* See PD_* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * SoC-specific Power Area Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct r8a779a0_sysc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const struct r8a779a0_sysc_area *areas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int num_areas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct r8a779a0_sysc_area r8a779a0_areas[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { "always-on", R8A779A0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { "a3e0", R8A779A0_PD_A3E0, R8A779A0_PD_ALWAYS_ON, PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { "a3e1", R8A779A0_PD_A3E1, R8A779A0_PD_ALWAYS_ON, PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { "a2e0d0", R8A779A0_PD_A2E0D0, R8A779A0_PD_A3E0, PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) { "a2e0d1", R8A779A0_PD_A2E0D1, R8A779A0_PD_A3E0, PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { "a2e1d0", R8A779A0_PD_A2E1D0, R8A779A0_PD_A3E1, PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { "a2e1d1", R8A779A0_PD_A2E1D1, R8A779A0_PD_A3E1, PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { "a1e0d0c0", R8A779A0_PD_A1E0D0C0, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { "a1e0d0c1", R8A779A0_PD_A1E0D0C1, R8A779A0_PD_A2E0D0, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { "a1e0d1c0", R8A779A0_PD_A1E0D1C0, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { "a1e0d1c1", R8A779A0_PD_A1E0D1C1, R8A779A0_PD_A2E0D1, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { "a1e1d0c0", R8A779A0_PD_A1E1D0C0, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { "a1e1d0c1", R8A779A0_PD_A1E1D0C1, R8A779A0_PD_A2E1D0, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { "a1e1d1c0", R8A779A0_PD_A1E1D1C0, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { "a1e1d1c1", R8A779A0_PD_A1E1D1C1, R8A779A0_PD_A2E1D1, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { "3dg-a", R8A779A0_PD_3DG_A, R8A779A0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { "3dg-b", R8A779A0_PD_3DG_B, R8A779A0_PD_3DG_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { "a3vip0", R8A779A0_PD_A3VIP0, R8A779A0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { "a3vip1", R8A779A0_PD_A3VIP1, R8A779A0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { "a3vip3", R8A779A0_PD_A3VIP3, R8A779A0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { "a3vip2", R8A779A0_PD_A3VIP2, R8A779A0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { "a3isp01", R8A779A0_PD_A3ISP01, R8A779A0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { "a3isp23", R8A779A0_PD_A3ISP23, R8A779A0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { "a3ir", R8A779A0_PD_A3IR, R8A779A0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { "a2cn0", R8A779A0_PD_A2CN0, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { "a2imp01", R8A779A0_PD_A2IMP01, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { "a2dp0", R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { "a2cv0", R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { "a2cv1", R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { "a2cv4", R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { "a2cv6", R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { "a2cn2", R8A779A0_PD_A2CN2, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { "a2imp23", R8A779A0_PD_A2IMP23, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { "a2dp1", R8A779A0_PD_A2DP0, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { "a2cv2", R8A779A0_PD_A2CV0, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { "a2cv3", R8A779A0_PD_A2CV1, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { "a2cv5", R8A779A0_PD_A2CV4, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { "a2cv7", R8A779A0_PD_A2CV6, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { "a2cn1", R8A779A0_PD_A2CN1, R8A779A0_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { "a1cnn0", R8A779A0_PD_A1CNN0, R8A779A0_PD_A2CN0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { "a1cnn2", R8A779A0_PD_A1CNN2, R8A779A0_PD_A2CN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { "a1dsp0", R8A779A0_PD_A1DSP0, R8A779A0_PD_A2CN2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { "a1cnn1", R8A779A0_PD_A1CNN1, R8A779A0_PD_A2CN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { "a1dsp1", R8A779A0_PD_A1DSP1, R8A779A0_PD_A2CN1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct r8a779a0_sysc_info r8a779a0_sysc_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .areas = r8a779a0_areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .num_areas = ARRAY_SIZE(r8a779a0_areas),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* SYSC Common */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SYSCSR 0x000 /* SYSC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SYSCPONSR(x) (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SYSCPOFFSR(x) (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SYSCISCR(x) (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SYSCIER(x) (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SYSCIMR(x) (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Power Domain Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PDRSR(n) (0x1000 + ((n) * 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PDRONCR(n) (0x1004 + ((n) * 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PDROFFCR(n) (0x1008 + ((n) * 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PDRESR(n) (0x100C + ((n) * 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* PWRON/PWROFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PWRON_PWROFF BIT(0) /* Power-ON/OFF request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* PDRESR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PDRESR_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* PDRSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PDRSR_OFF BIT(0) /* Power-OFF state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PDRSR_ON BIT(4) /* Power-ON state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PDRSR_OFF_STATE BIT(8) /* Processing Power-OFF sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PDRSR_ON_STATE BIT(12) /* Processing Power-ON sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SYSCSR_BUSY GENMASK(1, 0) /* All bit sets is not busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SYSCSR_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SYSCSR_DELAY_US 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PDRESR_RETRIES 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PDRESR_DELAY_US 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SYSCISR_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SYSCISR_DELAY_US 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define NUM_DOMAINS_EACH_REG BITS_PER_TYPE(u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void __iomem *r8a779a0_sysc_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static DEFINE_SPINLOCK(r8a779a0_sysc_lock); /* SMP CPUs + I/O devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int r8a779a0_sysc_pwr_on_off(u8 pdr, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int reg_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) reg_offs = PDRONCR(pdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) reg_offs = PDROFFCR(pdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Wait until SYSC is ready to accept a power request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCSR, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (val & SYSCSR_BUSY) == SYSCSR_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SYSCSR_DELAY_US, SYSCSR_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Submit power shutoff or power resume request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) iowrite32(PWRON_PWROFF, r8a779a0_sysc_base + reg_offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) iowrite32(isr_mask, r8a779a0_sysc_base + SYSCISCR(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val, !(val & isr_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SYSCISR_DELAY_US, SYSCISR_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int r8a779a0_sysc_power(u8 pdr, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int isr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned int reg_idx, bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) spin_lock_irqsave(&r8a779a0_sysc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg_idx = pdr / NUM_DOMAINS_EACH_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bit_idx = pdr % NUM_DOMAINS_EACH_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) isr_mask = BIT(bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * The interrupt source needs to be enabled, but masked, to prevent the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * CPU from receiving it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) iowrite32(ioread32(r8a779a0_sysc_base + SYSCIER(reg_idx)) | isr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) r8a779a0_sysc_base + SYSCIER(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) iowrite32(ioread32(r8a779a0_sysc_base + SYSCIMR(reg_idx)) | isr_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) r8a779a0_sysc_base + SYSCIMR(reg_idx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = clear_irq_flags(reg_idx, isr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Submit power shutoff or resume request until it was accepted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) for (k = 0; k < PDRESR_RETRIES; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = r8a779a0_sysc_pwr_on_off(pdr, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) status = ioread32(r8a779a0_sysc_base + PDRESR(pdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (!(status & PDRESR_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) udelay(PDRESR_DELAY_US);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (k == PDRESR_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Wait until the power shutoff or resume request has completed * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val, (val & isr_mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SYSCISR_DELAY_US, SYSCISR_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Clear interrupt flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = clear_irq_flags(reg_idx, isr_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) spin_unlock_irqrestore(&r8a779a0_sysc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pdr, ioread32(r8a779a0_sysc_base + SYSCISCR(reg_idx)), ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static bool r8a779a0_sysc_power_is_off(u8 pdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) st = ioread32(r8a779a0_sysc_base + PDRSR(pdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (st & PDRSR_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct r8a779a0_sysc_pd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct generic_pm_domain genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 pdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) char name[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static inline struct r8a779a0_sysc_pd *to_r8a779a0_pd(struct generic_pm_domain *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return container_of(d, struct r8a779a0_sysc_pd, genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int r8a779a0_sysc_pd_power_off(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pr_debug("%s: %s\n", __func__, genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return r8a779a0_sysc_power(pd->pdr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int r8a779a0_sysc_pd_power_on(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct r8a779a0_sysc_pd *pd = to_r8a779a0_pd(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pr_debug("%s: %s\n", __func__, genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return r8a779a0_sysc_power(pd->pdr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int __init r8a779a0_sysc_pd_setup(struct r8a779a0_sysc_pd *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct generic_pm_domain *genpd = &pd->genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) const char *name = pd->genpd.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (pd->flags & PD_CPU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * This domain contains a CPU core and therefore it should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * only be turned off if the CPU is not in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) pr_debug("PM domain %s contains %s\n", name, "CPU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) genpd->flags |= GENPD_FLAG_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } else if (pd->flags & PD_SCU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * This domain contains an SCU and cache-controller, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * therefore it should only be turned off if the CPU cores are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * not in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pr_debug("PM domain %s contains %s\n", name, "SCU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) genpd->flags |= GENPD_FLAG_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) } else if (pd->flags & PD_NO_CR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * This domain cannot be turned off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) genpd->flags |= GENPD_FLAG_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!(pd->flags & (PD_CPU | PD_SCU))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Enable Clock Domain for I/O devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) genpd->attach_dev = cpg_mssr_attach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) genpd->detach_dev = cpg_mssr_detach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) genpd->power_off = r8a779a0_sysc_pd_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) genpd->power_on = r8a779a0_sysc_pd_power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (pd->flags & (PD_CPU | PD_NO_CR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Skip CPUs (handled by SMP code) and areas without control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pr_debug("%s: Not touching %s\n", __func__, genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) goto finalize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!r8a779a0_sysc_power_is_off(pd->pdr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pr_debug("%s: %s is already powered\n", __func__, genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) goto finalize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) r8a779a0_sysc_power(pd->pdr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) finalize:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) error = pm_genpd_init(genpd, &simple_qos_governor, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pr_err("Failed to init PM domain %s: %d\n", name, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct of_device_id r8a779a0_sysc_matches[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct r8a779a0_pm_domains {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct genpd_onecell_data onecell_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct generic_pm_domain *domains[R8A779A0_PD_ALWAYS_ON + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct genpd_onecell_data *r8a779a0_sysc_onecell_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int __init r8a779a0_sysc_pd_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const struct r8a779a0_sysc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct r8a779a0_pm_domains *domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) np = of_find_matching_node_and_match(NULL, r8a779a0_sysc_matches, &match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) info = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pr_warn("%pOF: Cannot map regs\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) r8a779a0_sysc_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) domains = kzalloc(sizeof(*domains), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!domains) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) domains->onecell_data.domains = domains->domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) r8a779a0_sysc_onecell_data = &domains->onecell_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) for (i = 0; i < info->num_areas; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const struct r8a779a0_sysc_area *area = &info->areas[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct r8a779a0_sysc_pd *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!area->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Skip NULLified area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pd = kzalloc(sizeof(*pd) + strlen(area->name) + 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) error = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) strcpy(pd->name, area->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pd->genpd.name = pd->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pd->pdr = area->pdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pd->flags = area->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) error = r8a779a0_sysc_pd_setup(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) domains->domains[area->pdr] = &pd->genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (area->parent < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) error = pm_genpd_add_subdomain(domains->domains[area->parent],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) &pd->genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pr_warn("Failed to add PM subdomain %s to parent %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) area->name, area->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) goto out_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) out_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) early_initcall(r8a779a0_sysc_pd_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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