Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas R-Car V3M System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2017 Cogent Embedded Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/power/r8a77970-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "rcar-sysc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct rcar_sysc_area r8a77970_areas[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	{ "always-on",	    0, 0, R8A77970_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	{ "ca53-scu",	0x140, 0, R8A77970_PD_CA53_SCU,	R8A77970_PD_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	  PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	{ "ca53-cpu0",	0x200, 0, R8A77970_PD_CA53_CPU0, R8A77970_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	  PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	{ "ca53-cpu1",	0x200, 1, R8A77970_PD_CA53_CPU1, R8A77970_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	  PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	{ "a3ir",	0x180, 0, R8A77970_PD_A3IR,	R8A77970_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	{ "a2ir0",	0x400, 0, R8A77970_PD_A2IR0,	R8A77970_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	{ "a2ir1",	0x400, 1, R8A77970_PD_A2IR1,	R8A77970_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	{ "a2dp",	0x400, 2, R8A77970_PD_A2DP,	R8A77970_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	{ "a2cn",	0x400, 3, R8A77970_PD_A2CN,	R8A77970_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	{ "a2sc0",	0x400, 4, R8A77970_PD_A2SC0,	R8A77970_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	{ "a2sc1",	0x400, 5, R8A77970_PD_A2SC1,	R8A77970_PD_A3IR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const struct rcar_sysc_info r8a77970_sysc_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	.areas = r8a77970_areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	.num_areas = ARRAY_SIZE(r8a77970_areas),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	.extmask_offs = 0x1b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	.extmask_val = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };