Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas R-Car M3-W/W+ System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2016 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2018-2019 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/power/r8a7796-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "rcar-sysc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static struct rcar_sysc_area r8a7796_areas[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	{ "always-on",	    0, 0, R8A7796_PD_ALWAYS_ON,	-1, PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	{ "ca57-scu",	0x1c0, 0, R8A7796_PD_CA57_SCU,	R8A7796_PD_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	  PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	{ "ca57-cpu0",	 0x80, 0, R8A7796_PD_CA57_CPU0,	R8A7796_PD_CA57_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	  PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	{ "ca57-cpu1",	 0x80, 1, R8A7796_PD_CA57_CPU1,	R8A7796_PD_CA57_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	  PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	{ "ca53-scu",	0x140, 0, R8A7796_PD_CA53_SCU,	R8A7796_PD_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	  PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	{ "ca53-cpu0",	0x200, 0, R8A7796_PD_CA53_CPU0,	R8A7796_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	  PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	{ "ca53-cpu1",	0x200, 1, R8A7796_PD_CA53_CPU1,	R8A7796_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	  PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	{ "ca53-cpu2",	0x200, 2, R8A7796_PD_CA53_CPU2,	R8A7796_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	  PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	{ "ca53-cpu3",	0x200, 3, R8A7796_PD_CA53_CPU3,	R8A7796_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	  PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	{ "cr7",	0x240, 0, R8A7796_PD_CR7,	R8A7796_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	{ "a3vc",	0x380, 0, R8A7796_PD_A3VC,	R8A7796_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	{ "a2vc0",	0x3c0, 0, R8A7796_PD_A2VC0,	R8A7796_PD_A3VC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	{ "a2vc1",	0x3c0, 1, R8A7796_PD_A2VC1,	R8A7796_PD_A3VC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	{ "3dg-a",	0x100, 0, R8A7796_PD_3DG_A,	R8A7796_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	{ "3dg-b",	0x100, 1, R8A7796_PD_3DG_B,	R8A7796_PD_3DG_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	{ "a3ir",	0x180, 0, R8A7796_PD_A3IR,	R8A7796_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #ifdef CONFIG_SYSC_R8A77960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const struct rcar_sysc_info r8a77960_sysc_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	.areas = r8a7796_areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.num_areas = ARRAY_SIZE(r8a7796_areas),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif /* CONFIG_SYSC_R8A77960 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifdef CONFIG_SYSC_R8A77961
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int __init r8a77961_sysc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	rcar_sysc_nullify(r8a7796_areas, ARRAY_SIZE(r8a7796_areas),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			  R8A7796_PD_A2VC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const struct rcar_sysc_info r8a77961_sysc_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	.init = r8a77961_sysc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	.areas = r8a7796_areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	.num_areas = ARRAY_SIZE(r8a7796_areas),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	.extmask_offs = 0x2f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	.extmask_val = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif /* CONFIG_SYSC_R8A77961 */