^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas R-Car H3 System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-2017 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/power/r8a7795-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "rcar-sysc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static struct rcar_sysc_area r8a7795_areas[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) { "always-on", 0, 0, R8A7795_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) { "ca57-scu", 0x1c0, 0, R8A7795_PD_CA57_SCU, R8A7795_PD_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) { "ca57-cpu0", 0x80, 0, R8A7795_PD_CA57_CPU0, R8A7795_PD_CA57_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { "ca57-cpu1", 0x80, 1, R8A7795_PD_CA57_CPU1, R8A7795_PD_CA57_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { "ca57-cpu2", 0x80, 2, R8A7795_PD_CA57_CPU2, R8A7795_PD_CA57_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { "ca57-cpu3", 0x80, 3, R8A7795_PD_CA57_CPU3, R8A7795_PD_CA57_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { "ca53-scu", 0x140, 0, R8A7795_PD_CA53_SCU, R8A7795_PD_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { "ca53-cpu0", 0x200, 0, R8A7795_PD_CA53_CPU0, R8A7795_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { "ca53-cpu1", 0x200, 1, R8A7795_PD_CA53_CPU1, R8A7795_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { "ca53-cpu2", 0x200, 2, R8A7795_PD_CA53_CPU2, R8A7795_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { "ca53-cpu3", 0x200, 3, R8A7795_PD_CA53_CPU3, R8A7795_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { "a3vp", 0x340, 0, R8A7795_PD_A3VP, R8A7795_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { "cr7", 0x240, 0, R8A7795_PD_CR7, R8A7795_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { "a3vc", 0x380, 0, R8A7795_PD_A3VC, R8A7795_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* A2VC0 exists on ES1.x only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { "a2vc0", 0x3c0, 0, R8A7795_PD_A2VC0, R8A7795_PD_A3VC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { "a2vc1", 0x3c0, 1, R8A7795_PD_A2VC1, R8A7795_PD_A3VC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { "3dg-a", 0x100, 0, R8A7795_PD_3DG_A, R8A7795_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { "3dg-b", 0x100, 1, R8A7795_PD_3DG_B, R8A7795_PD_3DG_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { "3dg-c", 0x100, 2, R8A7795_PD_3DG_C, R8A7795_PD_3DG_B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { "3dg-d", 0x100, 3, R8A7795_PD_3DG_D, R8A7795_PD_3DG_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { "3dg-e", 0x100, 4, R8A7795_PD_3DG_E, R8A7795_PD_3DG_D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { "a3ir", 0x180, 0, R8A7795_PD_A3IR, R8A7795_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Fixups for R-Car H3 revisions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HAS_A2VC0 BIT(0) /* Power domain A2VC0 is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define NO_EXTMASK BIT(1) /* Missing SYSCEXTMASK register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct soc_device_attribute r8a7795_quirks_match[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .soc_id = "r8a7795", .revision = "ES1.*",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .data = (void *)(HAS_A2VC0 | NO_EXTMASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .soc_id = "r8a7795", .revision = "ES2.*",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .data = (void *)(NO_EXTMASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int __init r8a7795_sysc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const struct soc_device_attribute *attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 quirks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) attr = soc_device_match(r8a7795_quirks_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) quirks = (uintptr_t)attr->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!(quirks & HAS_A2VC0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) rcar_sysc_nullify(r8a7795_areas, ARRAY_SIZE(r8a7795_areas),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) R8A7795_PD_A2VC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (quirks & NO_EXTMASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) r8a7795_sysc_info.extmask_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct rcar_sysc_info r8a7795_sysc_info __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .init = r8a7795_sysc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .areas = r8a7795_areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .num_areas = ARRAY_SIZE(r8a7795_areas),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .extmask_offs = 0x2f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .extmask_val = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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