Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Renesas RZ/G2H System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2020 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Based on Renesas R-Car H3 System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2016-2017 Glider bvba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/power/r8a774e1-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "rcar-sysc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static const struct rcar_sysc_area r8a774e1_areas[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	{ "always-on",	    0, 0, R8A774E1_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	{ "ca57-scu",	0x1c0, 0, R8A774E1_PD_CA57_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	{ "ca57-cpu0",	 0x80, 0, R8A774E1_PD_CA57_CPU0, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	{ "ca57-cpu1",	 0x80, 1, R8A774E1_PD_CA57_CPU1, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	{ "ca57-cpu2",	 0x80, 2, R8A774E1_PD_CA57_CPU2, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	{ "ca57-cpu3",	 0x80, 3, R8A774E1_PD_CA57_CPU3, R8A774E1_PD_CA57_SCU, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	{ "ca53-scu",	0x140, 0, R8A774E1_PD_CA53_SCU, R8A774E1_PD_ALWAYS_ON, PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	{ "ca53-cpu0",	0x200, 0, R8A774E1_PD_CA53_CPU0, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	{ "ca53-cpu1",	0x200, 1, R8A774E1_PD_CA53_CPU1, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	{ "ca53-cpu2",	0x200, 2, R8A774E1_PD_CA53_CPU2, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	{ "ca53-cpu3",	0x200, 3, R8A774E1_PD_CA53_CPU3, R8A774E1_PD_CA53_SCU, PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	{ "a3vp",	0x340, 0, R8A774E1_PD_A3VP, R8A774E1_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	{ "a3vc",	0x380, 0, R8A774E1_PD_A3VC, R8A774E1_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	{ "a2vc1",	0x3c0, 1, R8A774E1_PD_A2VC1, R8A774E1_PD_A3VC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	{ "3dg-a",	0x100, 0, R8A774E1_PD_3DG_A, R8A774E1_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	{ "3dg-b",	0x100, 1, R8A774E1_PD_3DG_B, R8A774E1_PD_3DG_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	{ "3dg-c",	0x100, 2, R8A774E1_PD_3DG_C, R8A774E1_PD_3DG_B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	{ "3dg-d",	0x100, 3, R8A774E1_PD_3DG_D, R8A774E1_PD_3DG_C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	{ "3dg-e",	0x100, 4, R8A774E1_PD_3DG_E, R8A774E1_PD_3DG_D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const struct rcar_sysc_info r8a774e1_sysc_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	.areas = r8a774e1_areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	.num_areas = ARRAY_SIZE(r8a774e1_areas),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	.extmask_offs = 0x2f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	.extmask_val = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };