^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Renesas RZ/G2E System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on Renesas R-Car E3 System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/power/r8a774c0-sysc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "rcar-sysc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static struct rcar_sysc_area r8a774c0_areas[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) { "always-on", 0, 0, R8A774C0_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) { "ca53-scu", 0x140, 0, R8A774C0_PD_CA53_SCU, R8A774C0_PD_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PD_SCU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { "ca53-cpu0", 0x200, 0, R8A774C0_PD_CA53_CPU0, R8A774C0_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { "ca53-cpu1", 0x200, 1, R8A774C0_PD_CA53_CPU1, R8A774C0_PD_CA53_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PD_CPU_NOCR },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { "a3vc", 0x380, 0, R8A774C0_PD_A3VC, R8A774C0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { "a2vc1", 0x3c0, 1, R8A774C0_PD_A2VC1, R8A774C0_PD_A3VC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { "3dg-a", 0x100, 0, R8A774C0_PD_3DG_A, R8A774C0_PD_ALWAYS_ON },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { "3dg-b", 0x100, 1, R8A774C0_PD_3DG_B, R8A774C0_PD_3DG_A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Fixups for RZ/G2E ES1.0 revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct soc_device_attribute r8a774c0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { .soc_id = "r8a774c0", .revision = "ES1.0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int __init r8a774c0_sysc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (soc_device_match(r8a774c0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Fix incorrect 3DG hierarchy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) swap(r8a774c0_areas[6], r8a774c0_areas[7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) r8a774c0_areas[6].parent = R8A774C0_PD_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) r8a774c0_areas[7].parent = R8A774C0_PD_3DG_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const struct rcar_sysc_info r8a774c0_sysc_info __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .init = r8a774c0_sysc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .areas = r8a774c0_areas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .num_areas = ARRAY_SIZE(r8a774c0_areas),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .extmask_offs = 0x2f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .extmask_val = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };