^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/qcom-geni-se.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * DOC: Overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * controller. QUP Wrapper is designed to support various serial bus protocols
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * like UART, SPI, I2C, I3C, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * DOC: Hardware description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * GENI based QUP is a highly-flexible and programmable module for supporting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * QUP module can provide upto 8 serial interfaces, using its internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * serial engines. The actual configuration is determined by the target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * platform configuration. The protocol supported by each interface is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * determined by the firmware loaded to the serial engine. Each SE consists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * of a DMA Engine and GENI sub modules which enable serial engines to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * support FIFO and DMA modes of operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * |QUP Wrapper |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * | +----------------------------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * | | ... | | Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * <---Clock Perf.----+ +----+-----------------------+ | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * State Interface | | Serial Engine 1 | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * <--------AHB-------> | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * | | +----+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * <------SE IRQ------+ +----------------------------+ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Figure 1: GENI based QUP Wrapper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * The GENI submodules include primary and secondary sequencers which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * used to drive TX & RX operations. On serial interfaces that operate using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * master-slave model, primary sequencer drives both TX & RX operations. On
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * serial interfaces that operate using peer-to-peer model, primary sequencer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * drives TX operation and secondary sequencer drives RX operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * DOC: Software description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * GENI SE Wrapper driver is structured into 2 parts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * geni_wrapper represents QUP Wrapper controller. This part of the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * manages QUP Wrapper information such as hardware version, clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * performance table that is common to all the internal serial engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * geni_se represents serial engine. This part of the driver manages serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * engine information such as clocks, containing QUP Wrapper, etc. This part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * of driver also supports operations (eg. initialize the concerned serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * engine, select between FIFO and DMA mode of operation etc.) that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * common to all the serial engines and are independent of serial interfaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAX_CLK_PERF_LEVEL 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NUM_AHB_CLKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @dev: Device pointer of the QUP wrapper core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @base: Base address of this instance of QUP wrapper core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @ahb_clks: Handle to the primary & secondary AHB clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct geni_wrapper {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char * const icc_path_names[] = {"qup-core", "qup-config",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "qup-memory"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define QUP_HW_VER_REG 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Common SE registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GENI_INIT_CFG_REVISION 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GENI_S_INIT_CFG_REVISION 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GENI_OUTPUT_CTRL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GENI_CGC_CTRL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GENI_CLK_CTRL_RO 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GENI_IF_DISABLE_RO 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GENI_FW_S_REVISION_RO 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SE_GENI_BYTE_GRAN 0x254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SE_GENI_TX_PACKING_CFG0 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SE_GENI_TX_PACKING_CFG1 0x264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SE_GENI_RX_PACKING_CFG0 0x284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SE_GENI_RX_PACKING_CFG1 0x288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SE_GENI_M_GP_LENGTH 0x910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SE_GENI_S_GP_LENGTH 0x914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SE_DMA_TX_PTR_L 0xc30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SE_DMA_TX_PTR_H 0xc34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SE_DMA_TX_ATTR 0xc38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SE_DMA_TX_LEN 0xc3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SE_DMA_TX_IRQ_EN 0xc48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SE_DMA_TX_IRQ_EN_SET 0xc4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SE_DMA_TX_IRQ_EN_CLR 0xc50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SE_DMA_TX_LEN_IN 0xc54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SE_DMA_TX_MAX_BURST 0xc5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SE_DMA_RX_PTR_L 0xd30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SE_DMA_RX_PTR_H 0xd34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SE_DMA_RX_ATTR 0xd38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SE_DMA_RX_LEN 0xd3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SE_DMA_RX_IRQ_EN 0xd48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SE_DMA_RX_IRQ_EN_SET 0xd4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SE_DMA_RX_IRQ_EN_CLR 0xd50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SE_DMA_RX_LEN_IN 0xd54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SE_DMA_RX_MAX_BURST 0xd5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SE_DMA_RX_FLUSH 0xd60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SE_GSI_EVENT_EN 0xe18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SE_IRQ_EN 0xe1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SE_DMA_GENERAL_CFG 0xe30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* GENI_OUTPUT_CTRL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* GENI_CGC_CTRL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CFG_AHB_CLK_CGC_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define DATA_AHB_CLK_CGC_ON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SCLK_CGC_ON BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TX_CLK_CGC_ON BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RX_CLK_CGC_ON BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define EXT_CLK_CGC_ON BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PROG_RAM_HCLK_OFF BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PROG_RAM_SCLK_OFF BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DEFAULT_CGC_EN GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* SE_GSI_EVENT_EN fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DMA_RX_EVENT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DMA_TX_EVENT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GENI_M_EVENT_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GENI_S_EVENT_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* SE_IRQ_EN fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DMA_RX_IRQ_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DMA_TX_IRQ_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GENI_M_IRQ_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GENI_S_IRQ_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* SE_DMA_GENERAL_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DMA_RX_CLK_CGC_ON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DMA_TX_CLK_CGC_ON BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DMA_AHB_SLV_CFG_ON BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DUMMY_RX_NON_BUFFERABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RX_DMA_ZERO_PADDING_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RX_DMA_IRQ_DELAY_SHFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @se: Pointer to the corresponding serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Return: Hardware Version of the wrapper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 geni_se_get_qup_hw_version(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct geni_wrapper *wrapper = se->wrapper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) EXPORT_SYMBOL(geni_se_get_qup_hw_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void geni_se_io_set_mode(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) val = readl_relaxed(base + SE_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val |= GENI_M_IRQ_EN | GENI_S_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) val |= DMA_TX_IRQ_EN | DMA_RX_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel_relaxed(val, base + SE_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) val &= ~GENI_DMA_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writel_relaxed(0, base + SE_GSI_EVENT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void geni_se_io_init(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) val = readl_relaxed(base + GENI_CGC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val |= DEFAULT_CGC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel_relaxed(val, base + GENI_CGC_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void geni_se_irq_clear(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * geni_se_init() - Initialize the GENI serial engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @rx_wm: Receive watermark, in units of FIFO words.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * This function is used to initialize the GENI serial engine, configure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * receive watermark and ready-for-receive watermarks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) geni_se_irq_clear(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) geni_se_io_init(se->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) geni_se_io_set_mode(se->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val |= M_COMMON_GENI_M_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) val |= S_COMMON_GENI_S_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) EXPORT_SYMBOL(geni_se_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void geni_se_select_fifo_mode(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 proto = geni_se_read_proto(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) geni_se_irq_clear(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (proto != GENI_SE_UART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (proto != GENI_SE_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val |= S_CMD_DONE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val &= ~GENI_DMA_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void geni_se_select_dma_mode(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 proto = geni_se_read_proto(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) geni_se_irq_clear(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (proto != GENI_SE_UART) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (proto != GENI_SE_UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) val &= ~S_CMD_DONE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val |= GENI_DMA_MODE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * geni_se_select_mode() - Select the serial engine transfer mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @mode: Transfer mode to be selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) WARN_ON(mode != GENI_SE_FIFO && mode != GENI_SE_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case GENI_SE_FIFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) geni_se_select_fifo_mode(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case GENI_SE_DMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) geni_se_select_dma_mode(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case GENI_SE_INVALID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EXPORT_SYMBOL(geni_se_select_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * DOC: Overview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * of up to 4 operations, each operation represented by 4 configuration vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * of 10 bits programmed in GENI_TX_PACKING_CFG0 and GENI_TX_PACKING_CFG1 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * TX FIFO and in GENI_RX_PACKING_CFG0 and GENI_RX_PACKING_CFG1 for RX FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Refer to below examples for detailed bit-field description.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Example 1: word_size = 7, packing_mode = 4 x 8, msb_to_lsb = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * +-----------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * | | vec_0 | vec_1 | vec_2 | vec_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * +-----------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * | start | 0x6 | 0xe | 0x16 | 0x1e |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * | direction | 1 | 1 | 1 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * | length | 6 | 6 | 6 | 6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * | stop | 0 | 0 | 0 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * +-----------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Example 2: word_size = 15, packing_mode = 2 x 16, msb_to_lsb = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * +-----------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * | | vec_0 | vec_1 | vec_2 | vec_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * +-----------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * | start | 0x0 | 0x8 | 0x10 | 0x18 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * | direction | 0 | 0 | 0 | 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * | length | 7 | 6 | 7 | 6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * | stop | 0 | 0 | 0 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * +-----------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * Example 3: word_size = 23, packing_mode = 1 x 32, msb_to_lsb = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * +-----------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * | | vec_0 | vec_1 | vec_2 | vec_3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * +-----------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * | start | 0x16 | 0xe | 0x6 | 0x0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * | direction | 1 | 1 | 1 | 1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * | length | 7 | 7 | 6 | 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * | stop | 0 | 0 | 1 | 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * +-----------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define NUM_PACKING_VECTORS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PACKING_START_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define PACKING_DIR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PACKING_LEN_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define PACKING_STOP_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define PACKING_VECTOR_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * geni_se_config_packing() - Packing configuration of the serial engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * @se: Pointer to the concerned serial engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * @bpw: Bits of data per transfer word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * @pack_words: Number of words per fifo element.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * @tx_cfg: Flag to configure the TX Packing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * @rx_cfg: Flag to configure the RX Packing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * This function is used to configure the packing rules for the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) bool msb_to_lsb, bool tx_cfg, bool rx_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 cfg0, cfg1, cfg[NUM_PACKING_VECTORS] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int temp_bpw = bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int idx_start = msb_to_lsb ? bpw - 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int idx = idx_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ceil_bpw = ALIGN(bpw, BITS_PER_BYTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int iter = (ceil_bpw * pack_words) / BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (iter <= 0 || iter > NUM_PACKING_VECTORS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) for (i = 0; i < iter; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cfg[i] = idx << PACKING_START_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) cfg[i] |= msb_to_lsb << PACKING_DIR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cfg[i] |= len << PACKING_LEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (temp_bpw <= BITS_PER_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) idx = ((i + 1) * BITS_PER_BYTE) + idx_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) temp_bpw = bpw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) idx = idx + idx_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) temp_bpw = temp_bpw - BITS_PER_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) cfg[iter - 1] |= PACKING_STOP_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) cfg0 = cfg[0] | (cfg[1] << PACKING_VECTOR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) cfg1 = cfg[2] | (cfg[3] << PACKING_VECTOR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (tx_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (rx_cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * Number of protocol words in each FIFO entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * 0 - 4x8, four words in each entry, max word size of 8 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * 1 - 2x16, two words in each entry, max word size of 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * 2 - 1x32, one word in each entry, max word size of 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * 3 - undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (pack_words || bpw == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) EXPORT_SYMBOL(geni_se_config_packing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static void geni_se_clks_off(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct geni_wrapper *wrapper = se->wrapper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) clk_disable_unprepare(se->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) wrapper->ahb_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * geni_se_resources_off() - Turn off resources associated with the serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Return: 0 on success, standard Linux error codes on failure/error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int geni_se_resources_off(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (has_acpi_companion(se->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = pinctrl_pm_select_sleep_state(se->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) geni_se_clks_off(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) EXPORT_SYMBOL(geni_se_resources_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int geni_se_clks_on(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct geni_wrapper *wrapper = se->wrapper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) wrapper->ahb_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = clk_prepare_enable(se->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) wrapper->ahb_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * geni_se_resources_on() - Turn on resources associated with the serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Return: 0 on success, standard Linux error codes on failure/error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) int geni_se_resources_on(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (has_acpi_companion(se->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = geni_se_clks_on(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = pinctrl_pm_select_default_state(se->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) geni_se_clks_off(se);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) EXPORT_SYMBOL(geni_se_resources_on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * geni_se_clk_tbl_get() - Get the clock table to program DFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @tbl: Table in which the output is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * This function is called by the protocol drivers to determine the different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * clock frequencies supported by serial engine core clock. The protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * drivers use the output to determine the clock frequency index to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * programmed into DFS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * Return: number of valid performance levels in the table on success,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * standard Linux error codes on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) long freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (se->clk_perf_tbl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *tbl = se->clk_perf_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return se->num_clk_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) sizeof(*se->clk_perf_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!se->clk_perf_tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) for (i = 0; i < MAX_CLK_PERF_LEVEL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) freq = clk_round_rate(se->clk, freq + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (freq <= 0 || freq == se->clk_perf_tbl[i - 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) se->clk_perf_tbl[i] = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) se->num_clk_levels = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *tbl = se->clk_perf_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return se->num_clk_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) EXPORT_SYMBOL(geni_se_clk_tbl_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * @req_freq: Requested clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * @index: Index of the resultant frequency in the table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * @res_freq: Resultant frequency of the source clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * @exact: Flag to indicate exact multiple requirement of the requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * This function is called by the protocol drivers to determine the best match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * of the requested frequency as provided by the serial engine clock in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * to meet the performance requirements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * If we return success:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * - if @exact is true then @res_freq / <an_integer> == @req_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * - if @exact is false then @res_freq / <an_integer> <= @req_freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * Return: 0 on success, standard Linux error codes on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned int *index, unsigned long *res_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) bool exact)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned long *tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int num_clk_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned long best_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned long new_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (num_clk_levels < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return num_clk_levels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (num_clk_levels == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) best_delta = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) for (i = 0; i < num_clk_levels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) divider = DIV_ROUND_UP(tbl[i], req_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) new_delta = req_freq - tbl[i] / divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (new_delta < best_delta) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* We have a new best! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) *index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) *res_freq = tbl[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* If the new best is exact then we're done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (new_delta == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Record how close we got */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) best_delta = new_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (exact)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) EXPORT_SYMBOL(geni_se_clk_freq_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define GENI_SE_DMA_DONE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define GENI_SE_DMA_EOT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define GENI_SE_DMA_AHB_ERR_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define GENI_SE_DMA_EOT_BUF BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * @buf: Pointer to the TX buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * @len: Length of the TX buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * @iova: Pointer to store the mapped DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * This function is used to prepare the buffers for DMA TX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * Return: 0 on success, standard Linux error codes on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dma_addr_t *iova)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct geni_wrapper *wrapper = se->wrapper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (!wrapper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (dma_mapping_error(wrapper->dev, *iova))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) val = GENI_SE_DMA_DONE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) val |= GENI_SE_DMA_EOT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) val |= GENI_SE_DMA_AHB_ERR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) writel(len, se->base + SE_DMA_TX_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) EXPORT_SYMBOL(geni_se_tx_dma_prep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * @buf: Pointer to the RX buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * @len: Length of the RX buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * @iova: Pointer to store the mapped DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * This function is used to prepare the buffers for DMA RX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * Return: 0 on success, standard Linux error codes on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dma_addr_t *iova)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct geni_wrapper *wrapper = se->wrapper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!wrapper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (dma_mapping_error(wrapper->dev, *iova))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val = GENI_SE_DMA_DONE_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) val |= GENI_SE_DMA_EOT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) val |= GENI_SE_DMA_AHB_ERR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* RX does not have EOT buffer type bit. So just reset RX_ATTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) writel(len, se->base + SE_DMA_RX_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) EXPORT_SYMBOL(geni_se_rx_dma_prep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * @iova: DMA address of the TX buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * @len: Length of the TX buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * This function is used to unprepare the DMA buffers after DMA TX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct geni_wrapper *wrapper = se->wrapper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (iova && !dma_mapping_error(wrapper->dev, iova))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) EXPORT_SYMBOL(geni_se_tx_dma_unprep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * @se: Pointer to the concerned serial engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * @iova: DMA address of the RX buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * @len: Length of the RX buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * This function is used to unprepare the DMA buffers after DMA RX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct geni_wrapper *wrapper = se->wrapper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (iova && !dma_mapping_error(wrapper->dev, iova))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) EXPORT_SYMBOL(geni_se_rx_dma_unprep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int geni_icc_get(struct geni_se *se, const char *icc_ddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (has_acpi_companion(se->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (!icc_names[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (IS_ERR(se->icc_paths[i].path))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) err = PTR_ERR(se->icc_paths[i].path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (err != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) icc_names[i], err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) EXPORT_SYMBOL(geni_icc_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) int geni_icc_set_bw(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = icc_set_bw(se->icc_paths[i].path,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) icc_path_names[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) EXPORT_SYMBOL(geni_icc_set_bw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) void geni_icc_set_tag(struct geni_se *se, u32 tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) icc_set_tag(se->icc_paths[i].path, tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) EXPORT_SYMBOL(geni_icc_set_tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int geni_icc_enable(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = icc_enable(se->icc_paths[i].path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) icc_path_names[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) EXPORT_SYMBOL(geni_icc_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int geni_icc_disable(struct geni_se *se)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = icc_disable(se->icc_paths[i].path);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) icc_path_names[i], ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) EXPORT_SYMBOL(geni_icc_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int geni_se_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct geni_wrapper *wrapper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!wrapper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) wrapper->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) wrapper->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (IS_ERR(wrapper->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return PTR_ERR(wrapper->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!has_acpi_companion(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) wrapper->ahb_clks[0].id = "m-ahb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) wrapper->ahb_clks[1].id = "s-ahb";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_err(dev, "Err getting AHB clks %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_set_drvdata(dev, wrapper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_dbg(dev, "GENI SE Driver probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return devm_of_platform_populate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct of_device_id geni_se_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) { .compatible = "qcom,geni-se-qup", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) MODULE_DEVICE_TABLE(of, geni_se_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static struct platform_driver geni_se_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .name = "geni_se_qup",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .of_match_table = geni_se_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .probe = geni_se_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) module_platform_driver(geni_se_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MODULE_DESCRIPTION("GENI Serial Engine Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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