^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/soc/qcom/llcc-qcom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ACTIVATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DEACTIVATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ACT_CTRL_ACT_TRIG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ACT_CTRL_OPCODE_SHIFT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ATTR1_FIXED_SIZE_SHIFT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ATTR1_PRIORITY_SHIFT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ATTR1_MAX_CAP_SHIFT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ATTR0_RES_WAYS_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ATTR0_BONUS_WAYS_SHIFT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LLCC_STATUS_READ_DELAY 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CACHE_LINE_SIZE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LLCC_COMMON_STATUS0 0x0003000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LLCC_LB_CNT_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LLCC_LB_CNT_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX_CAP_TO_BYTES(n) (n * SZ_1K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BANK_OFFSET_STRIDE 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * llcc_slice_config - Data associated with the llcc slice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @usecase_id: Unique id for the client's use case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @slice_id: llcc slice id for each client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @max_cap: The maximum capacity of the cache slice provided in KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @priority: Priority of the client used to select victim line for replacement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @fixed_size: Boolean indicating if the slice has a fixed capacity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @bonus_ways: Bonus ways are additional ways to be used for any slice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * if client ends up using more than reserved cache ways. Bonus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * ways are allocated only if they are not reserved for some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * other client.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @res_ways: Reserved ways for the cache slice, the reserved ways cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * be used by any other client than the one its assigned to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @cache_mode: Each slice operates as a cache, this controls the mode of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * slice: normal or TCM(Tightly Coupled Memory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @probe_target_ways: Determines what ways to probe for access hit. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * configured to 1 only bonus and reserved ways are probed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * When configured to 0 all ways in llcc are probed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @dis_cap_alloc: Disable capacity based allocation for a client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @retain_on_pc: If this bit is set and client has maintained active vote
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * then the ways assigned to this client are not flushed on power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * collapse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @activate_on_init: Activate the slice immediately after it is programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct llcc_slice_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 usecase_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 slice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 max_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bool fixed_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 bonus_ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 res_ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 cache_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 probe_target_ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool dis_cap_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bool retain_on_pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bool activate_on_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct qcom_llcc_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const struct llcc_slice_config *sct_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct llcc_slice_config sc7180_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct llcc_slice_config sdm845_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct qcom_llcc_config sc7180_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .sct_data = sc7180_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .size = ARRAY_SIZE(sc7180_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const struct qcom_llcc_config sdm845_cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .sct_data = sdm845_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .size = ARRAY_SIZE(sdm845_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * llcc_slice_getd - get llcc slice descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @uid: usecase_id for the client
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * A pointer to llcc slice descriptor will be returned on success and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * and error pointer is returned on failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct llcc_slice_desc *llcc_slice_getd(u32 uid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct llcc_slice_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct llcc_slice_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 sz, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (IS_ERR(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ERR_CAST(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cfg = drv_data->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) sz = drv_data->cfg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) for (count = 0; cfg && count < sz; count++, cfg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (cfg->usecase_id == uid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (count == sz || !cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) desc = kzalloc(sizeof(*desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) desc->slice_id = cfg->slice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) desc->slice_size = cfg->max_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) EXPORT_SYMBOL_GPL(llcc_slice_getd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * llcc_slice_putd - llcc slice descritpor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @desc: Pointer to llcc slice descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void llcc_slice_putd(struct llcc_slice_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!IS_ERR_OR_NULL(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) EXPORT_SYMBOL_GPL(llcc_slice_putd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int llcc_update_act_ctrl(u32 sid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 act_ctrl_reg_val, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 act_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 slice_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (IS_ERR(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return PTR_ERR(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) status_reg = LLCC_TRP_STATUSn(sid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Set the ACTIVE trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) act_ctrl_reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Clear the ACTIVE trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) act_ctrl_reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) slice_status, !(slice_status & status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 0, LLCC_STATUS_READ_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * llcc_slice_activate - Activate the llcc slice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @desc: Pointer to llcc slice descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * A value of zero will be returned on success and a negative errno will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * be returned in error cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int llcc_slice_activate(struct llcc_slice_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 act_ctrl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (IS_ERR(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return PTR_ERR(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (IS_ERR_OR_NULL(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mutex_lock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (test_bit(desc->slice_id, drv_data->bitmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mutex_unlock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DEACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mutex_unlock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __set_bit(desc->slice_id, drv_data->bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mutex_unlock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) EXPORT_SYMBOL_GPL(llcc_slice_activate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * llcc_slice_deactivate - Deactivate the llcc slice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @desc: Pointer to llcc slice descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * A value of zero will be returned on success and a negative errno will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * be returned in error cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int llcc_slice_deactivate(struct llcc_slice_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 act_ctrl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (IS_ERR(drv_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return PTR_ERR(drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (IS_ERR_OR_NULL(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_lock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!test_bit(desc->slice_id, drv_data->bitmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mutex_unlock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mutex_unlock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __clear_bit(desc->slice_id, drv_data->bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mutex_unlock(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * llcc_get_slice_id - return the slice id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @desc: Pointer to llcc slice descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int llcc_get_slice_id(struct llcc_slice_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (IS_ERR_OR_NULL(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return desc->slice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) EXPORT_SYMBOL_GPL(llcc_get_slice_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * llcc_get_slice_size - return the slice id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @desc: Pointer to llcc slice descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (IS_ERR_OR_NULL(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return desc->slice_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) EXPORT_SYMBOL_GPL(llcc_get_slice_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int qcom_llcc_cfg_program(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 attr1_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 attr0_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 attr1_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 attr0_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 max_cap_cacheline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) const struct llcc_slice_config *llcc_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct llcc_slice_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) sz = drv_data->cfg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) llcc_table = drv_data->cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) for (i = 0; i < sz; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) attr1_val = llcc_table[i].cache_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) attr1_val |= llcc_table[i].probe_target_ways <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ATTR1_PROBE_TARGET_WAYS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) attr1_val |= llcc_table[i].fixed_size <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ATTR1_FIXED_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) attr1_val |= llcc_table[i].priority <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ATTR1_PRIORITY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* LLCC instances can vary for each target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * The SW writes to broadcast register which gets propagated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * to each llcc instace (llcc0,.. llccN).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Since the size of the memory is divided equally amongst the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * llcc instances, we need to configure the max cap accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = regmap_write(drv_data->bcast_regmap, attr1_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) attr1_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = regmap_write(drv_data->bcast_regmap, attr0_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) attr0_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (llcc_table[i].activate_on_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) desc.slice_id = llcc_table[i].slice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = llcc_slice_activate(&desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int qcom_llcc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Set the global pointer to a error code to avoid referencing it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) drv_data = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct regmap_config llcc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) base = devm_platform_ioremap_resource_byname(pdev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return ERR_CAST(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) llcc_regmap_config.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int qcom_llcc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 num_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct platform_device *llcc_edac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) const struct qcom_llcc_config *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const struct llcc_slice_config *llcc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!drv_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (IS_ERR(drv_data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = PTR_ERR(drv_data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) drv_data->bcast_regmap =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) qcom_llcc_init_mmio(pdev, "llcc_broadcast_base");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (IS_ERR(drv_data->bcast_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = PTR_ERR(drv_data->bcast_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) &num_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) num_banks &= LLCC_LB_CNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) num_banks >>= LLCC_LB_CNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) drv_data->num_banks = num_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) cfg = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) llcc_cfg = cfg->sct_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) sz = cfg->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) for (i = 0; i < sz; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (llcc_cfg[i].slice_id > drv_data->max_slices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) drv_data->max_slices = llcc_cfg[i].slice_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!drv_data->offsets) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) for (i = 0; i < num_banks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) drv_data->bitmap = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!drv_data->bitmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) drv_data->cfg = llcc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) drv_data->cfg_size = sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mutex_init(&drv_data->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) platform_set_drvdata(pdev, drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = qcom_llcc_cfg_program(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) drv_data->ecc_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (drv_data->ecc_irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) llcc_edac = platform_device_register_data(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "qcom_llcc_edac", -1, drv_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sizeof(*drv_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (IS_ERR(llcc_edac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(dev, "Failed to register llcc edac driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) drv_data = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct of_device_id qcom_llcc_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct platform_driver qcom_llcc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .name = "qcom-llcc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .of_match_table = qcom_llcc_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .probe = qcom_llcc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .remove = qcom_llcc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) module_platform_driver(qcom_llcc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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