^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2019, Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Register Offsets for RB-CPR and Bit Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* RBCPR Version Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_RBCPR_VERSION 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RBCPR_VER_2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FLAGS_IGNORE_1ST_IRQ_STATUS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* RBCPR Gate Count and Target Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_RBCPR_GCNT_TARGET(n) (0x60 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RBCPR_GCNT_TARGET_TARGET_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RBCPR_GCNT_TARGET_TARGET_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RBCPR_GCNT_TARGET_GCNT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RBCPR_GCNT_TARGET_GCNT_MASK GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* RBCPR Timer Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_RBCPR_TIMER_INTERVAL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_RBIF_TIMER_ADJUST 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RBIF_TIMER_ADJ_CONS_UP_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RBIF_TIMER_ADJ_CONS_UP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RBIF_TIMER_ADJ_CONS_DOWN_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RBIF_TIMER_ADJ_CONS_DOWN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RBIF_TIMER_ADJ_CLAMP_INT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RBIF_TIMER_ADJ_CLAMP_INT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* RBCPR Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_RBIF_LIMIT 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RBIF_LIMIT_CEILING_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RBIF_LIMIT_CEILING_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RBIF_LIMIT_FLOOR_BITS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RBIF_LIMIT_FLOOR_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RBIF_LIMIT_CEILING_DEFAULT RBIF_LIMIT_CEILING_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RBIF_LIMIT_FLOOR_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_RBIF_SW_VLEVEL 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RBIF_SW_VLEVEL_DEFAULT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_RBCPR_STEP_QUOT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RBCPR_STEP_QUOT_STEPQUOT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RBCPR_STEP_QUOT_IDLE_CLK_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RBCPR_STEP_QUOT_IDLE_CLK_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* RBCPR Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_RBCPR_CTL 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RBCPR_CTL_LOOP_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RBCPR_CTL_TIMER_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RBCPR_CTL_SW_AUTO_CONT_ACK_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RBCPR_CTL_COUNT_MODE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RBCPR_CTL_UP_THRESHOLD_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RBCPR_CTL_UP_THRESHOLD_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RBCPR_CTL_DN_THRESHOLD_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RBCPR_CTL_DN_THRESHOLD_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* RBCPR Ack/Nack Response */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_RBIF_CONT_ACK_CMD 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_RBIF_CONT_NACK_CMD 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* RBCPR Result status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG_RBCPR_RESULT_0 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RBCPR_RESULT0_BUSY_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RBCPR_RESULT0_BUSY_MASK BIT(RBCPR_RESULT0_BUSY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RBCPR_RESULT0_ERROR_LT0_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RBCPR_RESULT0_ERROR_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RBCPR_RESULT0_ERROR_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RBCPR_RESULT0_ERROR_STEPS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define RBCPR_RESULT0_ERROR_STEPS_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RBCPR_RESULT0_STEP_UP_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* RBCPR Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_RBIF_IRQ_EN(n) (0x100 + 4 * (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_RBIF_IRQ_CLEAR 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_RBIF_IRQ_STATUS 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CPR_INT_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CPR_INT_MIN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CPR_INT_DOWN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CPR_INT_MID BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CPR_INT_UP BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CPR_INT_MAX BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CPR_INT_CLAMP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CPR_INT_ALL (CPR_INT_DONE | CPR_INT_MIN | CPR_INT_DOWN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CPR_INT_MID | CPR_INT_UP | CPR_INT_MAX | CPR_INT_CLAMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CPR_INT_DEFAULT (CPR_INT_UP | CPR_INT_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CPR_NUM_RING_OSC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* CPR eFuse parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CPR_FUSE_TARGET_QUOT_BITS_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CPR_FUSE_MIN_QUOT_DIFF 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FUSE_REVISION_UNKNOWN (-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum voltage_change_dir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) NO_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct cpr_fuse {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) char *ring_osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) char *init_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) char *quotient;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) char *quotient_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct fuse_corner_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ref_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int max_volt_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int max_quot_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* fuse quot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int quot_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int quot_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int quot_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* fuse quot_offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int quot_offset_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int quot_offset_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct cpr_fuses {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int init_voltage_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int init_voltage_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct fuse_corner_data *fuse_corner_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct corner_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct cpr_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned int num_fuse_corners;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int min_diff_quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int *step_quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int timer_delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int timer_cons_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int timer_cons_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned int up_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int down_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int idle_clocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int gcnt_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int vdd_apc_step_up_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int vdd_apc_step_down_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int clamp_timer_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct cpr_fuses cpr_fuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bool reduce_to_fuse_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) bool reduce_to_corner_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct acc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct reg_sequence *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct reg_sequence *settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int num_regs_per_fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct cpr_acc_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) const struct cpr_desc *cpr_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const struct acc_desc *acc_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct fuse_corner {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int step_quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) const struct reg_sequence *accs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int num_accs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 ring_osc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct corner {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int last_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int quot_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 save_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 save_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct fuse_corner *fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct cpr_drv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int num_corners;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int ref_clk_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct generic_pm_domain pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct device *attached_cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct corner *corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct regulator *vdd_apc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct clk *cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct regmap *tcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bool loop_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 gcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct fuse_corner *fuse_corners;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct corner *corners;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) const struct cpr_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const struct acc_desc *acc_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) const struct cpr_fuse *cpr_fuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct dentry *debugfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static bool cpr_is_allowed(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return !drv->loop_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) writel_relaxed(value, drv->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static u32 cpr_read(struct cpr_drv *drv, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return readl_relaxed(drv->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) val = readl_relaxed(drv->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) val |= value & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writel_relaxed(val, drv->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void cpr_irq_clr(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void cpr_irq_clr_nack(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cpr_irq_clr(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void cpr_irq_clr_ack(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) cpr_irq_clr(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cpr_masked_write(drv, REG_RBCPR_CTL, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) const struct cpr_desc *desc = drv->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Program Consecutive Up & Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mask = RBIF_TIMER_ADJ_CONS_UP_MASK | RBIF_TIMER_ADJ_CONS_DOWN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) cpr_masked_write(drv, REG_RBCPR_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) RBCPR_CTL_SW_AUTO_CONT_ACK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) corner->save_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) cpr_irq_set(drv, corner->save_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (cpr_is_allowed(drv) && corner->max_uV > corner->min_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) val = RBCPR_CTL_LOOP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void cpr_ctl_disable(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) cpr_irq_set(drv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) RBCPR_CTL_SW_AUTO_CONT_ACK_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) RBIF_TIMER_ADJ_CONS_UP_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) RBIF_TIMER_ADJ_CONS_DOWN_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cpr_irq_clr(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static bool cpr_ctl_is_enabled(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) reg_val = cpr_read(drv, REG_RBCPR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return reg_val & RBCPR_CTL_LOOP_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static bool cpr_ctl_is_busy(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) reg_val = cpr_read(drv, REG_RBCPR_RESULT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return reg_val & RBCPR_RESULT0_BUSY_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 gcnt, ctl, irq, ro_sel, step_quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct fuse_corner *fuse = corner->fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) const struct cpr_desc *desc = drv->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ro_sel = fuse->ring_osc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) gcnt = drv->gcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) gcnt |= fuse->quot - corner->quot_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Program the step quotient and idle clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) step_quot = desc->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) step_quot |= fuse->step_quot & RBCPR_STEP_QUOT_STEPQUOT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Clear the target quotient value and gate count of all ROs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) for (i = 0; i < CPR_NUM_RING_OSC; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ctl = corner->save_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) cpr_write(drv, REG_RBCPR_CTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) irq = corner->save_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) cpr_irq_set(drv, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_dbg(drv->dev, "gcnt = %#08x, ctl = %#08x, irq = %#08x\n", gcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ctl, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct fuse_corner *end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (f == end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (f < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) for (f += 1; f <= end; f++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (f -= 1; f >= end; f--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int cpr_pre_voltage(struct cpr_drv *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct fuse_corner *fuse_corner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) enum voltage_change_dir dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (drv->tcsr && dir == DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int cpr_post_voltage(struct cpr_drv *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct fuse_corner *fuse_corner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) enum voltage_change_dir dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (drv->tcsr && dir == UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int cpr_scale_voltage(struct cpr_drv *drv, struct corner *corner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int new_uV, enum voltage_change_dir dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct fuse_corner *fuse_corner = corner->fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ret = cpr_pre_voltage(drv, fuse_corner, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ret = regulator_set_voltage(drv->vdd_apc, new_uV, new_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dev_err_ratelimited(drv->dev, "failed to set apc voltage %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) new_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = cpr_post_voltage(drv, fuse_corner, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static unsigned int cpr_get_cur_perf_state(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return drv->corner ? drv->corner - drv->corners + 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 val, error_steps, reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int last_uV, new_uV, step_uV, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct corner *corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) const struct cpr_desc *desc = drv->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (dir != UP && dir != DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) step_uV = regulator_get_linear_step(drv->vdd_apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!step_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) corner = drv->corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) val = cpr_read(drv, REG_RBCPR_RESULT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) error_steps &= RBCPR_RESULT0_ERROR_STEPS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) last_uV = corner->last_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (dir == UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (desc->clamp_timer_interval &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) error_steps < desc->up_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * Handle the case where another measurement started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * after the interrupt was triggered due to a core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * exiting from power collapse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) error_steps = max(desc->up_threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) desc->vdd_apc_step_up_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (last_uV >= corner->max_uV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) cpr_irq_clr_nack(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Maximize the UP threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val = reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) cpr_ctl_modify(drv, reg_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Disable UP interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (error_steps > desc->vdd_apc_step_up_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) error_steps = desc->vdd_apc_step_up_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Calculate new voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) new_uV = last_uV + error_steps * step_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) new_uV = min(new_uV, corner->max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_dbg(drv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "UP: -> new_uV: %d last_uV: %d perf state: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) new_uV, last_uV, cpr_get_cur_perf_state(drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (desc->clamp_timer_interval &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) error_steps < desc->down_threshold) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Handle the case where another measurement started
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * after the interrupt was triggered due to a core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * exiting from power collapse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) error_steps = max(desc->down_threshold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) desc->vdd_apc_step_down_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (last_uV <= corner->min_uV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cpr_irq_clr_nack(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Enable auto nack down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cpr_ctl_modify(drv, reg_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Disable DOWN interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (error_steps > desc->vdd_apc_step_down_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) error_steps = desc->vdd_apc_step_down_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Calculate new voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) new_uV = last_uV - error_steps * step_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) new_uV = max(new_uV, corner->min_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_dbg(drv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "DOWN: -> new_uV: %d last_uV: %d perf state: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) new_uV, last_uV, cpr_get_cur_perf_state(drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = cpr_scale_voltage(drv, corner, new_uV, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) cpr_irq_clr_nack(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) drv->corner->last_uV = new_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (dir == UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Disable auto nack down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Restore default threshold for UP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) val = desc->up_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) cpr_ctl_modify(drv, reg_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Re-enable default interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) cpr_irq_set(drv, CPR_INT_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) cpr_irq_clr_ack(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static irqreturn_t cpr_irq_handler(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct cpr_drv *drv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) const struct cpr_desc *desc = drv->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) irqreturn_t ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mutex_lock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev_dbg(drv->dev, "IRQ_STATUS = %#02x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!cpr_ctl_is_enabled(drv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_dbg(drv->dev, "CPR is disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } else if (cpr_ctl_is_busy(drv) && !desc->clamp_timer_interval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_dbg(drv->dev, "CPR measurement is not ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) } else if (!cpr_is_allowed(drv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) val = cpr_read(drv, REG_RBCPR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_err_ratelimited(drv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "Interrupt broken? RBCPR_CTL = %#02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * Following sequence of handling is as per each IRQ's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (val & CPR_INT_UP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) cpr_scale(drv, UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) } else if (val & CPR_INT_DOWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) cpr_scale(drv, DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } else if (val & CPR_INT_MIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) cpr_irq_clr_nack(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) } else if (val & CPR_INT_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) cpr_irq_clr_nack(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else if (val & CPR_INT_MID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* RBCPR_CTL_SW_AUTO_CONT_ACK_EN is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_dbg(drv->dev, "IRQ occurred for Mid Flag\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_dbg(drv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "IRQ occurred for unknown flag (%#08x)\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Save register values for the corner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) cpr_corner_save(drv, drv->corner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) mutex_unlock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int cpr_enable(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = regulator_enable(drv->vdd_apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) mutex_lock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (cpr_is_allowed(drv) && drv->corner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) cpr_irq_clr(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) cpr_corner_restore(drv, drv->corner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) cpr_ctl_enable(drv, drv->corner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mutex_unlock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int cpr_disable(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) mutex_lock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (cpr_is_allowed(drv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) cpr_ctl_disable(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) cpr_irq_clr(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mutex_unlock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return regulator_disable(drv->vdd_apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int cpr_config(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 val, gcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct corner *corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) const struct cpr_desc *desc = drv->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Disable interrupt and CPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) cpr_write(drv, REG_RBIF_IRQ_EN(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) cpr_write(drv, REG_RBCPR_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Program the default HW ceiling, floor and vlevel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) val = (RBIF_LIMIT_CEILING_DEFAULT & RBIF_LIMIT_CEILING_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) << RBIF_LIMIT_CEILING_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) val |= RBIF_LIMIT_FLOOR_DEFAULT & RBIF_LIMIT_FLOOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) cpr_write(drv, REG_RBIF_LIMIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * Clear the target quotient value and gate count of all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * ring oscillators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) for (i = 0; i < CPR_NUM_RING_OSC; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Init and save gcnt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) gcnt = (drv->ref_clk_khz * desc->gcnt_us) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) gcnt = gcnt & RBCPR_GCNT_TARGET_GCNT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) gcnt <<= RBCPR_GCNT_TARGET_GCNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) drv->gcnt = gcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Program the delay count for the timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) val = (drv->ref_clk_khz * desc->timer_delay_us) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_dbg(drv->dev, "Timer count: %#0x (for %d us)\n", val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) desc->timer_delay_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /* Program Consecutive Up & Down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) val = desc->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) val |= desc->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) val |= desc->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) cpr_write(drv, REG_RBIF_TIMER_ADJUST, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Program the control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) val = desc->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) val |= desc->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) cpr_write(drv, REG_RBCPR_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) for (i = 0; i < drv->num_corners; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) corner = &drv->corners[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) corner->save_ctl = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) corner->save_irq = CPR_INT_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) cpr_irq_set(drv, CPR_INT_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val = cpr_read(drv, REG_RBCPR_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (val <= RBCPR_VER_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int cpr_set_performance_state(struct generic_pm_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsigned int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct corner *corner, *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) enum voltage_change_dir dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) int ret = 0, new_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) mutex_lock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_dbg(drv->dev, "%s: setting perf state: %u (prev state: %u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) __func__, state, cpr_get_cur_perf_state(drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * Determine new corner we're going to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * Remove one since lowest performance state is 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) corner = drv->corners + state - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) end = &drv->corners[drv->num_corners - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (corner > end || corner < drv->corners) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Determine direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (drv->corner > corner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dir = DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) else if (drv->corner < corner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dir = UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dir = NO_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (cpr_is_allowed(drv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) new_uV = corner->last_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) new_uV = corner->uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (cpr_is_allowed(drv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) cpr_ctl_disable(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ret = cpr_scale_voltage(drv, corner, new_uV, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (cpr_is_allowed(drv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) cpr_irq_clr(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (drv->corner != corner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) cpr_corner_restore(drv, corner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) cpr_ctl_enable(drv, corner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) drv->corner = corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mutex_unlock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int cpr_read_efuse(struct device *dev, const char *cname, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct nvmem_cell *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ssize_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) char *ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) *data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) cell = nvmem_cell_get(dev, cname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (IS_ERR(cell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (PTR_ERR(cell) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_err(dev, "undefined cell %s\n", cname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return PTR_ERR(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = nvmem_cell_read(cell, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) nvmem_cell_put(cell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (IS_ERR(ret)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_err(dev, "can't read cell %s\n", cname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return PTR_ERR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) *data |= ret[i] << (8 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) kfree(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_dbg(dev, "efuse read(%s) = %x, bytes %zd\n", cname, *data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) cpr_populate_ring_osc_idx(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct fuse_corner *fuse = drv->fuse_corners;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct fuse_corner *end = fuse + drv->desc->num_fuse_corners;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) const struct cpr_fuse *fuses = drv->cpr_fuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) for (; fuse < end; fuse++, fuses++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = cpr_read_efuse(drv->dev, fuses->ring_osc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) fuse->ring_osc_idx = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int cpr_read_fuse_uV(const struct cpr_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) const struct fuse_corner_data *fdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) const char *init_v_efuse,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) int step_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int step_size_uV, steps, uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ret = cpr_read_efuse(drv->dev, init_v_efuse, &bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) steps = bits & ~BIT(desc->cpr_fuses.init_voltage_width - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Not two's complement.. instead highest bit is sign bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (bits & BIT(desc->cpr_fuses.init_voltage_width - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) steps = -steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) step_size_uV = desc->cpr_fuses.init_voltage_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) uV = fdata->ref_uV + steps * step_size_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return DIV_ROUND_UP(uV, step_volt) * step_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int cpr_fuse_corner_init(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) const struct cpr_desc *desc = drv->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) const struct cpr_fuse *fuses = drv->cpr_fuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) const struct acc_desc *acc_desc = drv->acc_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) unsigned int step_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct fuse_corner_data *fdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct fuse_corner *fuse, *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) const struct reg_sequence *accs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) accs = acc_desc->settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) step_volt = regulator_get_linear_step(drv->vdd_apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!step_volt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Populate fuse_corner members */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) fuse = drv->fuse_corners;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) end = &fuse[desc->num_fuse_corners - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) fdata = desc->cpr_fuses.fuse_corner_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) for (i = 0; fuse <= end; fuse++, fuses++, i++, fdata++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * Update SoC voltages: platforms might choose a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * regulators than the one used to characterize the algorithms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * (ie, init_voltage_step).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) fdata->min_uV = roundup(fdata->min_uV, step_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) fdata->max_uV = roundup(fdata->max_uV, step_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* Populate uV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) uV = cpr_read_fuse_uV(desc, fdata, fuses->init_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) step_volt, drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (uV < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) fuse->min_uV = fdata->min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) fuse->max_uV = fdata->max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (fuse == end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * Allow the highest fuse corner's PVS voltage to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * define the ceiling voltage for that corner in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * to support SoC's in which variable ceiling values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * are required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) end->max_uV = max(end->max_uV, end->uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Populate target quotient by scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = cpr_read_efuse(drv->dev, fuses->quotient, &fuse->quot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) fuse->quot *= fdata->quot_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) fuse->quot += fdata->quot_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) fuse->quot += fdata->quot_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) fuse->step_quot = desc->step_quot[fuse->ring_osc_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Populate acc settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) fuse->accs = accs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) fuse->num_accs = acc_desc->num_regs_per_fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) accs += acc_desc->num_regs_per_fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * Restrict all fuse corner PVS voltages based upon per corner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * ceiling and floor voltages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (fuse->uV > fuse->max_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) fuse->uV = fuse->max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) else if (fuse->uV < fuse->min_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) fuse->uV = fuse->min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = regulator_is_supported_voltage(drv->vdd_apc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) fuse->min_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) fuse->min_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_err(drv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) "min uV: %d (fuse corner: %d) not supported by regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) fuse->min_uV, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = regulator_is_supported_voltage(drv->vdd_apc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) fuse->max_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) fuse->max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dev_err(drv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) "max uV: %d (fuse corner: %d) not supported by regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) fuse->max_uV, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_dbg(drv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "fuse corner %d: [%d %d %d] RO%hhu quot %d squot %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) i, fuse->min_uV, fuse->uV, fuse->max_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) fuse->ring_osc_idx, fuse->quot, fuse->step_quot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int cpr_calculate_scaling(const char *quot_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct cpr_drv *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) const struct fuse_corner_data *fdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) const struct corner *corner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u32 quot_diff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) unsigned long freq_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) const struct fuse_corner *fuse, *prev_fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) fuse = corner->fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) prev_fuse = fuse - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (quot_offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret = cpr_read_efuse(drv->dev, quot_offset, "_diff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) quot_diff *= fdata->quot_offset_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) quot_diff += fdata->quot_offset_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) quot_diff = fuse->quot - prev_fuse->quot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) freq_diff = fuse->max_freq - prev_fuse->max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) freq_diff /= 1000000; /* Convert to MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) scaling = 1000 * quot_diff / freq_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return min(scaling, fdata->max_quot_scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int cpr_interpolate(const struct corner *corner, int step_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) const struct fuse_corner_data *fdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) unsigned long f_high, f_low, f_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int uV_high, uV_low, uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) u64 temp, temp_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) const struct fuse_corner *fuse, *prev_fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) fuse = corner->fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) prev_fuse = fuse - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) f_high = fuse->max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) f_low = prev_fuse->max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) uV_high = fuse->uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) uV_low = prev_fuse->uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) f_diff = fuse->max_freq - corner->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * Don't interpolate in the wrong direction. This could happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * if the adjusted fuse voltage overlaps with the previous fuse's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * adjusted voltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (f_high <= f_low || uV_high <= uV_low || f_high <= corner->freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return corner->uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) temp = f_diff * (uV_high - uV_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) temp = div64_ul(temp, f_high - f_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) * max_volt_scale has units of uV/MHz while freq values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * have units of Hz. Divide by 1000000 to convert to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) temp_limit = f_diff * fdata->max_volt_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) do_div(temp_limit, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) uV = uV_high - min(temp, temp_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return roundup(uV, step_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static unsigned int cpr_get_fuse_corner(struct dev_pm_opp *opp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) unsigned int fuse_corner = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) np = dev_pm_opp_get_of_node(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (of_property_read_u32(np, "qcom,opp-fuse-level", &fuse_corner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) pr_err("%s: missing 'qcom,opp-fuse-level' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static unsigned long cpr_get_opp_hz_for_req(struct dev_pm_opp *ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct device *cpu_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) u64 rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct device_node *ref_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct device_node *desc_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct device_node *child_np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct device_node *child_req_np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) desc_np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!desc_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ref_np = dev_pm_opp_get_of_node(ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (!ref_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) goto out_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) of_node_put(child_req_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) child_np = of_get_next_available_child(desc_np, child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) child_req_np = of_parse_phandle(child_np, "required-opps", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) } while (child_np && child_req_np != ref_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (child_np && child_req_np == ref_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) of_property_read_u64(child_np, "opp-hz", &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) of_node_put(child_req_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) of_node_put(child_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) of_node_put(ref_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) out_ref:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) of_node_put(desc_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return (unsigned long) rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static int cpr_corner_init(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) const struct cpr_desc *desc = drv->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) const struct cpr_fuse *fuses = drv->cpr_fuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) int i, level, scaling = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) unsigned int fnum, fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) const char *quot_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct fuse_corner *fuse, *prev_fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct corner *corner, *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct corner_data *cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) const struct fuse_corner_data *fdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) bool apply_scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) unsigned long freq_diff, freq_diff_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) int step_volt = regulator_get_linear_step(drv->vdd_apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (!step_volt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) corner = drv->corners;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) end = &corner[drv->num_corners - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) cdata = devm_kcalloc(drv->dev, drv->num_corners,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) sizeof(struct corner_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (!cdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) * Store maximum frequency for each fuse corner based on the frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * plan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) for (level = 1; level <= drv->num_corners; level++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) opp = dev_pm_opp_find_level_exact(&drv->pd.dev, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (IS_ERR(opp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) fc = cpr_get_fuse_corner(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (!fc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) fnum = fc - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) freq = cpr_get_opp_hz_for_req(opp, drv->attached_cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (!freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) cdata[level - 1].fuse_corner = fnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) cdata[level - 1].freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) fuse = &drv->fuse_corners[fnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev_dbg(drv->dev, "freq: %lu level: %u fuse level: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) freq, dev_pm_opp_get_level(opp) - 1, fnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (freq > fuse->max_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) fuse->max_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) * Get the quotient adjustment scaling factor, according to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * / (freq(corner_N) - freq(corner_N-1)), max_factor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * QUOT(corner_N): quotient read from fuse for fuse corner N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * QUOT(corner_N-1): quotient read from fuse for fuse corner (N - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * freq(corner_N): max frequency in MHz supported by fuse corner N
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * freq(corner_N-1): max frequency in MHz supported by fuse corner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * (N - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * Then walk through the corners mapped to each fuse corner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) * and calculate the quotient adjustment for each one using the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * following formula:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * quot_adjust = (freq_max - freq_corner) * scaling / 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * freq_max: max frequency in MHz supported by the fuse corner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) * freq_corner: frequency in MHz corresponding to the corner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * scaling: calculated from above equation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) * + +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * | v |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * q | f c o | f c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * u | c l | c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * o | f t | f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) * t | c a | c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * | c f g | c f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * | e |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * +--------------- +----------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * 0 1 2 3 4 5 6 0 1 2 3 4 5 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * corner corner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * c = corner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * f = fuse corner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) for (apply_scaling = false, i = 0; corner <= end; corner++, i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) fnum = cdata[i].fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) fdata = &desc->cpr_fuses.fuse_corner_data[fnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) quot_offset = fuses[fnum].quotient_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) fuse = &drv->fuse_corners[fnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (fnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) prev_fuse = &drv->fuse_corners[fnum - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) prev_fuse = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) corner->fuse_corner = fuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) corner->freq = cdata[i].freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) corner->uV = fuse->uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) scaling = cpr_calculate_scaling(quot_offset, drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) fdata, corner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (scaling < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) apply_scaling = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) } else if (corner->freq == fuse->max_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* This is a fuse corner; don't scale anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) apply_scaling = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (apply_scaling) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) freq_diff = fuse->max_freq - corner->freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) freq_diff_mhz = freq_diff / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) corner->quot_adjust = scaling * freq_diff_mhz / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) corner->uV = cpr_interpolate(corner, step_volt, fdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) corner->max_uV = fuse->max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) corner->min_uV = fuse->min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) corner->last_uV = corner->uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* Reduce the ceiling voltage if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) corner->max_uV = corner->uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) corner->max_uV = max(corner->min_uV, fuse->uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dev_dbg(drv->dev, "corner %d: [%d %d %d] quot %d\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) corner->min_uV, corner->uV, corner->max_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) fuse->quot - corner->quot_adjust);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static const struct cpr_fuse *cpr_get_fuses(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) const struct cpr_desc *desc = drv->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) struct cpr_fuse *fuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) fuses = devm_kcalloc(drv->dev, desc->num_fuse_corners,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) sizeof(struct cpr_fuse),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (!fuses)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) for (i = 0; i < desc->num_fuse_corners; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) char tbuf[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) snprintf(tbuf, 32, "cpr_ring_osc%d", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) fuses[i].ring_osc = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (!fuses[i].ring_osc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) snprintf(tbuf, 32, "cpr_init_voltage%d", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) fuses[i].init_voltage = devm_kstrdup(drv->dev, tbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (!fuses[i].init_voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) snprintf(tbuf, 32, "cpr_quotient%d", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) fuses[i].quotient = devm_kstrdup(drv->dev, tbuf, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (!fuses[i].quotient)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) snprintf(tbuf, 32, "cpr_quotient_offset%d", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) fuses[i].quotient_offset = devm_kstrdup(drv->dev, tbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (!fuses[i].quotient_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return fuses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static void cpr_set_loop_allowed(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) drv->loop_disabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static int cpr_init_parameters(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) const struct cpr_desc *desc = drv->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) clk = clk_get(drv->dev, "ref");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) drv->ref_clk_khz = clk_get_rate(clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (desc->timer_cons_up > RBIF_TIMER_ADJ_CONS_UP_MASK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) desc->timer_cons_down > RBIF_TIMER_ADJ_CONS_DOWN_MASK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) desc->up_threshold > RBCPR_CTL_UP_THRESHOLD_MASK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) desc->down_threshold > RBCPR_CTL_DN_THRESHOLD_MASK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) desc->idle_clocks > RBCPR_STEP_QUOT_IDLE_CLK_MASK ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) desc->clamp_timer_interval > RBIF_TIMER_ADJ_CLAMP_INT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) dev_dbg(drv->dev, "up threshold = %u, down threshold = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) desc->up_threshold, desc->down_threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int cpr_find_initial_corner(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) const struct corner *end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct corner *iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (!drv->cpu_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev_err(drv->dev, "cannot get rate from NULL clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) end = &drv->corners[drv->num_corners - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) rate = clk_get_rate(drv->cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * Some bootloaders set a CPU clock frequency that is not defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * in the OPP table. When running at an unlisted frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * cpufreq_online() will change to the OPP which has the lowest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * frequency, at or above the unlisted frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * Since cpufreq_online() always "rounds up" in the case of an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * unlisted frequency, this function always "rounds down" in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * of an unlisted frequency. That way, when cpufreq_online()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * triggers the first ever call to cpr_set_performance_state(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * it will correctly determine the direction as UP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) for (iter = drv->corners; iter <= end; iter++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (iter->freq > rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (iter->freq == rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) drv->corner = iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (iter->freq < rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) drv->corner = iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (!drv->corner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) dev_err(drv->dev, "boot up corner not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dev_dbg(drv->dev, "boot up perf state: %u\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static const struct cpr_desc qcs404_cpr_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .num_fuse_corners = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .min_diff_quot = CPR_FUSE_MIN_QUOT_DIFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .step_quot = (int []){ 25, 25, 25, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .timer_delay_us = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .timer_cons_up = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .timer_cons_down = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .up_threshold = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .down_threshold = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .idle_clocks = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .gcnt_us = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .vdd_apc_step_up_limit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .vdd_apc_step_down_limit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .cpr_fuses = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .init_voltage_step = 8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .init_voltage_width = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .fuse_corner_data = (struct fuse_corner_data[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* fuse corner 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .ref_uV = 1224000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .max_uV = 1224000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .min_uV = 1048000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .max_volt_scale = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .max_quot_scale = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .quot_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .quot_scale = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .quot_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .quot_offset_scale = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .quot_offset_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* fuse corner 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .ref_uV = 1288000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .max_uV = 1288000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .min_uV = 1048000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .max_volt_scale = 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .max_quot_scale = 1400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .quot_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .quot_scale = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .quot_adjust = -20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .quot_offset_scale = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) .quot_offset_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* fuse corner 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .ref_uV = 1352000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .max_uV = 1384000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .min_uV = 1088000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .max_volt_scale = 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .max_quot_scale = 1400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .quot_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .quot_scale = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .quot_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .quot_offset_scale = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .quot_offset_adjust = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static const struct acc_desc qcs404_acc_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .settings = (struct reg_sequence[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) { 0xb120, 0x1041040 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) { 0xb124, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) { 0xb120, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) { 0xb124, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) { 0xb120, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) { 0xb124, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .config = (struct reg_sequence[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) { 0xb138, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) { 0xb130, 0x5555 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .num_regs_per_fuse = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static const struct cpr_acc_desc qcs404_cpr_acc_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .cpr_desc = &qcs404_cpr_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .acc_desc = &qcs404_acc_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static unsigned int cpr_get_performance_state(struct generic_pm_domain *genpd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) struct dev_pm_opp *opp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return dev_pm_opp_get_level(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static int cpr_power_off(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return cpr_disable(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static int cpr_power_on(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return cpr_enable(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static int cpr_pd_attach_dev(struct generic_pm_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) struct cpr_drv *drv = container_of(domain, struct cpr_drv, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) const struct acc_desc *acc_desc = drv->acc_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) mutex_lock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) dev_dbg(drv->dev, "attach callback for: %s\n", dev_name(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) * This driver only supports scaling voltage for a CPU cluster
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * where all CPUs in the cluster share a single regulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * Therefore, save the struct device pointer only for the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) * CPU device that gets attached. There is no need to do any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) * additional initialization when further CPUs get attached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (drv->attached_cpu_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) * cpr_scale_voltage() requires the direction (if we are changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * to a higher or lower OPP). The first time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * cpr_set_performance_state() is called, there is no previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * performance state defined. Therefore, we call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * cpr_find_initial_corner() that gets the CPU clock frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * set by the bootloader, so that we can determine the direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) * the first time cpr_set_performance_state() is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) drv->cpu_clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (IS_ERR(drv->cpu_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) ret = PTR_ERR(drv->cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) dev_err(drv->dev, "could not get cpu clk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) drv->attached_cpu_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) dev_dbg(drv->dev, "using cpu clk from: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) dev_name(drv->attached_cpu_dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * Everything related to (virtual) corners has to be initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) * here, when attaching to the power domain, since we need to know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) * the maximum frequency for each fuse corner, and this is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) * available after the cpufreq driver has attached to us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) * The reason for this is that we need to know the highest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) * frequency associated with each fuse corner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ret = dev_pm_opp_get_opp_count(&drv->pd.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) dev_err(drv->dev, "could not get OPP count\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) drv->num_corners = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (drv->num_corners < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) dev_err(drv->dev, "need at least 2 OPPs to use CPR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) drv->corners = devm_kcalloc(drv->dev, drv->num_corners,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) sizeof(*drv->corners),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) if (!drv->corners) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ret = cpr_corner_init(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) cpr_set_loop_allowed(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret = cpr_init_parameters(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* Configure CPR HW but keep it disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) ret = cpr_config(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) ret = cpr_find_initial_corner(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (acc_desc->config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) regmap_multi_reg_write(drv->tcsr, acc_desc->config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) acc_desc->num_regs_per_fuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) /* Enable ACC if required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (acc_desc->enable_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) acc_desc->enable_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) acc_desc->enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) dev_info(drv->dev, "driver initialized with %u OPPs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) drv->num_corners);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) mutex_unlock(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static int cpr_debug_info_show(struct seq_file *s, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) u32 gcnt, ro_sel, ctl, irq_status, reg, error_steps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) u32 step_dn, step_up, error, error_lt0, busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct cpr_drv *drv = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) struct fuse_corner *fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) struct corner *corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) corner = drv->corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) fuse_corner = corner->fuse_corner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) seq_printf(s, "corner, current_volt = %d uV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) corner->last_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) ro_sel = fuse_corner->ring_osc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) gcnt = cpr_read(drv, REG_RBCPR_GCNT_TARGET(ro_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) seq_printf(s, "rbcpr_gcnt_target (%u) = %#02X\n", ro_sel, gcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ctl = cpr_read(drv, REG_RBCPR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) seq_printf(s, "rbcpr_ctl = %#02X\n", ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) irq_status = cpr_read(drv, REG_RBIF_IRQ_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) seq_printf(s, "rbcpr_irq_status = %#02X\n", irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) reg = cpr_read(drv, REG_RBCPR_RESULT_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) seq_printf(s, "rbcpr_result_0 = %#02X\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) step_dn = reg & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) step_up = (reg >> RBCPR_RESULT0_STEP_UP_SHIFT) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) seq_printf(s, " [step_dn = %u", step_dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) seq_printf(s, ", step_up = %u", step_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) error_steps = (reg >> RBCPR_RESULT0_ERROR_STEPS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) & RBCPR_RESULT0_ERROR_STEPS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) seq_printf(s, ", error_steps = %u", error_steps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) error = (reg >> RBCPR_RESULT0_ERROR_SHIFT) & RBCPR_RESULT0_ERROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) seq_printf(s, ", error = %u", error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) error_lt0 = (reg >> RBCPR_RESULT0_ERROR_LT0_SHIFT) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) seq_printf(s, ", error_lt_0 = %u", error_lt0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) busy = (reg >> RBCPR_RESULT0_BUSY_SHIFT) & 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) seq_printf(s, ", busy = %u]\n", busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) DEFINE_SHOW_ATTRIBUTE(cpr_debug_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static void cpr_debugfs_init(struct cpr_drv *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) drv->debugfs = debugfs_create_dir("qcom_cpr", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) debugfs_create_file("debug_info", 0444, drv->debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) drv, &cpr_debug_info_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static int cpr_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct cpr_drv *drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) const struct cpr_acc_desc *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) u32 cpr_rev = FUSE_REVISION_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) data = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (!data || !data->cpr_desc || !data->acc_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (!drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) drv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) drv->desc = data->cpr_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) drv->acc_desc = data->acc_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) drv->fuse_corners = devm_kcalloc(dev, drv->desc->num_fuse_corners,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) sizeof(*drv->fuse_corners),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (!drv->fuse_corners)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) np = of_parse_phandle(dev->of_node, "acc-syscon", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) drv->tcsr = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (IS_ERR(drv->tcsr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return PTR_ERR(drv->tcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) drv->base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (IS_ERR(drv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return PTR_ERR(drv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) drv->vdd_apc = devm_regulator_get(dev, "vdd-apc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (IS_ERR(drv->vdd_apc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return PTR_ERR(drv->vdd_apc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) * Initialize fuse corners, since it simply depends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * on data in efuses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) * Everything related to (virtual) corners has to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) * initialized after attaching to the power domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) * since it depends on the CPU's OPP table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ret = cpr_read_efuse(dev, "cpr_fuse_revision", &cpr_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) drv->cpr_fuses = cpr_get_fuses(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (IS_ERR(drv->cpr_fuses))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return PTR_ERR(drv->cpr_fuses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ret = cpr_populate_ring_osc_idx(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ret = cpr_fuse_corner_init(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) mutex_init(&drv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ret = devm_request_threaded_irq(dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) cpr_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) IRQF_ONESHOT | IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) "cpr", drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) drv->pd.name = devm_kstrdup_const(dev, dev->of_node->full_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (!drv->pd.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) drv->pd.power_off = cpr_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) drv->pd.power_on = cpr_power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) drv->pd.set_performance_state = cpr_set_performance_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) drv->pd.opp_to_performance_state = cpr_get_performance_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) drv->pd.attach_dev = cpr_pd_attach_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) ret = pm_genpd_init(&drv->pd, NULL, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) ret = of_genpd_add_provider_simple(dev->of_node, &drv->pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) platform_set_drvdata(pdev, drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) cpr_debugfs_init(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static int cpr_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) struct cpr_drv *drv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (cpr_is_allowed(drv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) cpr_ctl_disable(drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) cpr_irq_set(drv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) of_genpd_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) pm_genpd_remove(&drv->pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) debugfs_remove_recursive(drv->debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static const struct of_device_id cpr_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) { .compatible = "qcom,qcs404-cpr", .data = &qcs404_cpr_acc_desc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) MODULE_DEVICE_TABLE(of, cpr_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static struct platform_driver cpr_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .probe = cpr_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .remove = cpr_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .name = "qcom-cpr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .of_match_table = cpr_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) module_platform_driver(cpr_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) MODULE_DESCRIPTION("Core Power Reduction (CPR) driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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