^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/soc/mediatek/infracfg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/power/mt2701-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/power/mt2712-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/power/mt6797-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/power/mt7622-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <dt-bindings/power/mt7623a-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <dt-bindings/power/mt8173-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MTK_POLL_DELAY_US 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MTK_POLL_TIMEOUT USEC_PER_SEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MTK_SCPD_FWAIT_SRAM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPM_VDE_PWR_CON 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPM_MFG_PWR_CON 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPM_VEN_PWR_CON 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPM_ISP_PWR_CON 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPM_DIS_PWR_CON 0x023c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPM_CONN_PWR_CON 0x0280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPM_VEN2_PWR_CON 0x0298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPM_AUDIO_PWR_CON 0x029c /* MT8173, MT2712 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPM_BDP_PWR_CON 0x029c /* MT2701 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPM_ETH_PWR_CON 0x02a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPM_HIF_PWR_CON 0x02a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPM_IFR_MSC_PWR_CON 0x02a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPM_MFG_2D_PWR_CON 0x02c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPM_MFG_ASYNC_PWR_CON 0x02c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPM_USB_PWR_CON 0x02cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPM_USB2_PWR_CON 0x02d4 /* MT2712 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPM_ETHSYS_PWR_CON 0x02e0 /* MT7622 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPM_HIF0_PWR_CON 0x02e4 /* MT7622 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPM_HIF1_PWR_CON 0x02e8 /* MT7622 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPM_WB_PWR_CON 0x02ec /* MT7622 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPM_PWR_STATUS 0x060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPM_PWR_STATUS_2ND 0x0610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PWR_RST_B_BIT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PWR_ISO_BIT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PWR_ON_BIT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PWR_ON_2ND_BIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PWR_CLK_DIS_BIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PWR_STATUS_CONN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PWR_STATUS_DISP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PWR_STATUS_MFG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PWR_STATUS_ISP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PWR_STATUS_VDEC BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PWR_STATUS_BDP BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PWR_STATUS_ETH BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PWR_STATUS_HIF BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PWR_STATUS_IFR_MSC BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PWR_STATUS_USB2 BIT(19) /* MT2712 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PWR_STATUS_VENC_LT BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PWR_STATUS_VENC BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PWR_STATUS_MFG_2D BIT(22) /* MT8173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PWR_STATUS_MFG_ASYNC BIT(23) /* MT8173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PWR_STATUS_AUDIO BIT(24) /* MT8173, MT2712 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PWR_STATUS_USB BIT(25) /* MT8173, MT2712 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PWR_STATUS_ETHSYS BIT(24) /* MT7622 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PWR_STATUS_HIF0 BIT(25) /* MT7622 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PWR_STATUS_WB BIT(27) /* MT7622 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum clk_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) CLK_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CLK_MM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) CLK_MFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CLK_VENC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CLK_VENC_LT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CLK_ETHIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) CLK_VDEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CLK_HIFSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CLK_JPGDEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CLK_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) CLK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const char * const clk_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "mfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "venc_lt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "ethif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "hif_sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "jpgdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MAX_CLKS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * struct scp_domain_data - scp domain data for power on/off flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @name: The domain name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @sta_mask: The mask for power on/off status bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @ctl_offs: The offset for main power control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @sram_pdn_bits: The mask for sram power control bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @sram_pdn_ack_bits: The mask for sram power control acked bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @bus_prot_mask: The mask for single step bus protection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @clk_id: The basic clocks required by this power domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @caps: The flag for active wake-up action.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct scp_domain_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 sta_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int ctl_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 sram_pdn_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 sram_pdn_ack_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 bus_prot_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum clk_id clk_id[MAX_CLKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct scp_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct generic_pm_domain genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct scp *scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct clk *clk[MAX_CLKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct scp_domain_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct regulator *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct scp_ctrl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int pwr_sta_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int pwr_sta2nd_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct scp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct scp_domain *domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct genpd_onecell_data pd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct regmap *infracfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct scp_ctrl_reg ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool bus_prot_reg_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct scp_subdomain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int origin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int subdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct scp_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const struct scp_domain_data *domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int num_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const struct scp_subdomain *subdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int num_subdomains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const struct scp_ctrl_reg regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool bus_prot_reg_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int scpsys_domain_is_on(struct scp_domain *scpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct scp *scp = scpd->scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 status = readl(scp->base + scp->ctrl_reg.pwr_sta_offs) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) scpd->data->sta_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 status2 = readl(scp->base + scp->ctrl_reg.pwr_sta2nd_offs) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) scpd->data->sta_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * A domain is on when both status bits are set. If only one is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * return an error. This happens while powering up a domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (status && status2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!status && !status2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int scpsys_regulator_enable(struct scp_domain *scpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!scpd->supply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return regulator_enable(scpd->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int scpsys_regulator_disable(struct scp_domain *scpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!scpd->supply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return regulator_disable(scpd->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void scpsys_clk_disable(struct clk *clk[], int max_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (i = max_num - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) clk_disable_unprepare(clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int scpsys_clk_enable(struct clk *clk[], int max_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (i = 0; i < max_num && clk[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = clk_prepare_enable(clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) scpsys_clk_disable(clk, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val = readl(ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) val &= ~scpd->data->sram_pdn_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * MT7622_POWER_DOMAIN_WB and thus just a trivial setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * is applied here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) usleep_range(12000, 12100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Either wait until SRAM_PDN_ACK all 1 or 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int ret = readl_poll_timeout(ctl_addr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (tmp & pdn_ack) == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val = readl(ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val |= scpd->data->sram_pdn_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Either wait until SRAM_PDN_ACK all 1 or 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return readl_poll_timeout(ctl_addr, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) (tmp & pdn_ack) == pdn_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int scpsys_bus_protect_enable(struct scp_domain *scpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct scp *scp = scpd->scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!scpd->data->bus_prot_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return mtk_infracfg_set_bus_protection(scp->infracfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) scpd->data->bus_prot_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) scp->bus_prot_reg_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int scpsys_bus_protect_disable(struct scp_domain *scpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct scp *scp = scpd->scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!scpd->data->bus_prot_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return mtk_infracfg_clear_bus_protection(scp->infracfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) scpd->data->bus_prot_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) scp->bus_prot_reg_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int scpsys_power_on(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct scp *scp = scpd->scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = scpsys_regulator_enable(scpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = scpsys_clk_enable(scpd->clk, MAX_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* subsys power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) val = readl(ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) val |= PWR_ON_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) val |= PWR_ON_2ND_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* wait until PWR_ACK = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = readx_poll_timeout(scpsys_domain_is_on, scpd, tmp, tmp > 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) goto err_pwr_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) val &= ~PWR_CLK_DIS_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) val &= ~PWR_ISO_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) val |= PWR_RST_B_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = scpsys_sram_enable(scpd, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto err_pwr_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = scpsys_bus_protect_disable(scpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) goto err_pwr_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err_pwr_ack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) scpsys_clk_disable(scpd->clk, MAX_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) scpsys_regulator_disable(scpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int scpsys_power_off(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct scp *scp = scpd->scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) int ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = scpsys_bus_protect_enable(scpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = scpsys_sram_disable(scpd, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* subsys power off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) val = readl(ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) val |= PWR_ISO_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) val &= ~PWR_RST_B_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) val |= PWR_CLK_DIS_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) val &= ~PWR_ON_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) val &= ~PWR_ON_2ND_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writel(val, ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* wait until PWR_ACK = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = readx_poll_timeout(scpsys_domain_is_on, scpd, tmp, tmp == 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) scpsys_clk_disable(scpd->clk, MAX_CLKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = scpsys_regulator_disable(scpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(scp->dev, "Failed to power off domain %s\n", genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void init_clks(struct platform_device *pdev, struct clk **clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) for (i = CLK_NONE + 1; i < CLK_MAX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct scp *init_scp(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) const struct scp_domain_data *scp_domain_data, int num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) const struct scp_ctrl_reg *scp_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) bool bus_prot_reg_update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct genpd_onecell_data *pd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct scp *scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct clk *clk[CLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!scp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) scp->bus_prot_reg_update = bus_prot_reg_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) scp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) scp->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (IS_ERR(scp->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ERR_CAST(scp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) scp->domains = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) num, sizeof(*scp->domains), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!scp->domains)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pd_data = &scp->pd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pd_data->domains = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) num, sizeof(*pd_data->domains), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!pd_data->domains)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "infracfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (IS_ERR(scp->infracfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PTR_ERR(scp->infracfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ERR_CAST(scp->infracfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct scp_domain *scpd = &scp->domains[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) const struct scp_domain_data *data = &scp_domain_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) scpd->supply = devm_regulator_get_optional(&pdev->dev, data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (IS_ERR(scpd->supply)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (PTR_ERR(scpd->supply) == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) scpd->supply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return ERR_CAST(scpd->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) pd_data->num_domains = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) init_clks(pdev, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct scp_domain *scpd = &scp->domains[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct generic_pm_domain *genpd = &scpd->genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const struct scp_domain_data *data = &scp_domain_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pd_data->domains[i] = genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) scpd->scp = scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) scpd->data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct clk *c = clk[data->clk_id[j]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (IS_ERR(c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_err(&pdev->dev, "%s: clk unavailable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return ERR_CAST(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) scpd->clk[j] = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) genpd->name = data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) genpd->power_off = scpsys_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) genpd->power_on = scpsys_power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ACTIVE_WAKEUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) genpd->flags |= GENPD_FLAG_ACTIVE_WAKEUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static void mtk_register_power_domains(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct scp *scp, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct genpd_onecell_data *pd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct scp_domain *scpd = &scp->domains[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct generic_pm_domain *genpd = &scpd->genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) bool on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Initially turn on all domains to make the domains usable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * with !CONFIG_PM and to get the hardware in sync with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * software. The unused domains will be switched off during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * late_init time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) on = !WARN_ON(genpd->power_on(genpd) < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) pm_genpd_init(genpd, NULL, !on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * We are not allowed to fail here since there is no way to unregister
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * a power domain. Once registered above we have to keep the domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pd_data = &scp->pd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = of_genpd_add_provider_onecell(pdev->dev.of_node, pd_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(&pdev->dev, "Failed to add OF provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * MT2701 power domain support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const struct scp_domain_data scp_domain_data_mt2701[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) [MT2701_POWER_DOMAIN_CONN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .name = "conn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .sta_mask = PWR_STATUS_CONN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .ctl_offs = SPM_CONN_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MT2701_TOP_AXI_PROT_EN_CONN_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [MT2701_POWER_DOMAIN_DISP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .name = "disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .sta_mask = PWR_STATUS_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .ctl_offs = SPM_DIS_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .clk_id = {CLK_MM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) [MT2701_POWER_DOMAIN_MFG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .name = "mfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .sta_mask = PWR_STATUS_MFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .ctl_offs = SPM_MFG_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .sram_pdn_ack_bits = GENMASK(12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .clk_id = {CLK_MFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) [MT2701_POWER_DOMAIN_VDEC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .sta_mask = PWR_STATUS_VDEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .ctl_offs = SPM_VDE_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .sram_pdn_ack_bits = GENMASK(12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .clk_id = {CLK_MM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) [MT2701_POWER_DOMAIN_ISP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .name = "isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .sta_mask = PWR_STATUS_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .ctl_offs = SPM_ISP_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .sram_pdn_ack_bits = GENMASK(13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .clk_id = {CLK_MM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) [MT2701_POWER_DOMAIN_BDP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .name = "bdp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .sta_mask = PWR_STATUS_BDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .ctl_offs = SPM_BDP_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) [MT2701_POWER_DOMAIN_ETH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .name = "eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .sta_mask = PWR_STATUS_ETH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .ctl_offs = SPM_ETH_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .clk_id = {CLK_ETHIF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) [MT2701_POWER_DOMAIN_HIF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .name = "hif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .sta_mask = PWR_STATUS_HIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .ctl_offs = SPM_HIF_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .clk_id = {CLK_ETHIF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) [MT2701_POWER_DOMAIN_IFR_MSC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .name = "ifr_msc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .sta_mask = PWR_STATUS_IFR_MSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .ctl_offs = SPM_IFR_MSC_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * MT2712 power domain support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const struct scp_domain_data scp_domain_data_mt2712[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) [MT2712_POWER_DOMAIN_MM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .name = "mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .sta_mask = PWR_STATUS_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .ctl_offs = SPM_DIS_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .sram_pdn_bits = GENMASK(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .sram_pdn_ack_bits = GENMASK(12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .clk_id = {CLK_MM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) [MT2712_POWER_DOMAIN_VDEC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .name = "vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .sta_mask = PWR_STATUS_VDEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .ctl_offs = SPM_VDE_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .sram_pdn_bits = GENMASK(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .sram_pdn_ack_bits = GENMASK(12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .clk_id = {CLK_MM, CLK_VDEC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [MT2712_POWER_DOMAIN_VENC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .name = "venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .sta_mask = PWR_STATUS_VENC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .ctl_offs = SPM_VEN_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .clk_id = {CLK_MM, CLK_VENC, CLK_JPGDEC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [MT2712_POWER_DOMAIN_ISP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .name = "isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .sta_mask = PWR_STATUS_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .ctl_offs = SPM_ISP_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .sram_pdn_ack_bits = GENMASK(13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .clk_id = {CLK_MM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) [MT2712_POWER_DOMAIN_AUDIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .name = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .sta_mask = PWR_STATUS_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .ctl_offs = SPM_AUDIO_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .clk_id = {CLK_AUDIO},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [MT2712_POWER_DOMAIN_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .name = "usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .sta_mask = PWR_STATUS_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .ctl_offs = SPM_USB_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .sram_pdn_bits = GENMASK(10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .sram_pdn_ack_bits = GENMASK(14, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [MT2712_POWER_DOMAIN_USB2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .name = "usb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .sta_mask = PWR_STATUS_USB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .ctl_offs = SPM_USB2_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .sram_pdn_bits = GENMASK(10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .sram_pdn_ack_bits = GENMASK(14, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [MT2712_POWER_DOMAIN_MFG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .name = "mfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .sta_mask = PWR_STATUS_MFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .ctl_offs = SPM_MFG_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .sram_pdn_bits = GENMASK(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .sram_pdn_ack_bits = GENMASK(16, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .clk_id = {CLK_MFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [MT2712_POWER_DOMAIN_MFG_SC1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .name = "mfg_sc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .sta_mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .ctl_offs = 0x02c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .sram_pdn_bits = GENMASK(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .sram_pdn_ack_bits = GENMASK(16, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [MT2712_POWER_DOMAIN_MFG_SC2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .name = "mfg_sc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .sta_mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .ctl_offs = 0x02c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .sram_pdn_bits = GENMASK(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .sram_pdn_ack_bits = GENMASK(16, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [MT2712_POWER_DOMAIN_MFG_SC3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .name = "mfg_sc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .sta_mask = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .ctl_offs = 0x01f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .sram_pdn_bits = GENMASK(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .sram_pdn_ack_bits = GENMASK(16, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const struct scp_subdomain scp_subdomain_mt2712[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VDEC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_VENC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {MT2712_POWER_DOMAIN_MM, MT2712_POWER_DOMAIN_ISP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {MT2712_POWER_DOMAIN_MFG, MT2712_POWER_DOMAIN_MFG_SC1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {MT2712_POWER_DOMAIN_MFG_SC1, MT2712_POWER_DOMAIN_MFG_SC2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * MT6797 power domain support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct scp_domain_data scp_domain_data_mt6797[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [MT6797_POWER_DOMAIN_VDEC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .name = "vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .sta_mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .ctl_offs = 0x300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .sram_pdn_bits = GENMASK(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .sram_pdn_ack_bits = GENMASK(12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .clk_id = {CLK_VDEC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [MT6797_POWER_DOMAIN_VENC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .name = "venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .sta_mask = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .ctl_offs = 0x304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [MT6797_POWER_DOMAIN_ISP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .name = "isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .sta_mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .ctl_offs = 0x308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .sram_pdn_bits = GENMASK(9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .sram_pdn_ack_bits = GENMASK(13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [MT6797_POWER_DOMAIN_MM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .name = "mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .sta_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .ctl_offs = 0x30C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .sram_pdn_bits = GENMASK(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .sram_pdn_ack_bits = GENMASK(12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .clk_id = {CLK_MM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .bus_prot_mask = (BIT(1) | BIT(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [MT6797_POWER_DOMAIN_AUDIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .name = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .sta_mask = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .ctl_offs = 0x314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [MT6797_POWER_DOMAIN_MFG_ASYNC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .name = "mfg_async",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .sta_mask = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .ctl_offs = 0x334,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .sram_pdn_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .sram_pdn_ack_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .clk_id = {CLK_MFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [MT6797_POWER_DOMAIN_MJC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .name = "mjc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .sta_mask = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .ctl_offs = 0x310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .sram_pdn_bits = GENMASK(8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .sram_pdn_ack_bits = GENMASK(12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define SPM_PWR_STATUS_MT6797 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define SPM_PWR_STATUS_2ND_MT6797 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const struct scp_subdomain scp_subdomain_mt6797[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_VDEC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_ISP},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_VENC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {MT6797_POWER_DOMAIN_MM, MT6797_POWER_DOMAIN_MJC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * MT7622 power domain support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct scp_domain_data scp_domain_data_mt7622[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [MT7622_POWER_DOMAIN_ETHSYS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .name = "ethsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .sta_mask = PWR_STATUS_ETHSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .ctl_offs = SPM_ETHSYS_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [MT7622_POWER_DOMAIN_HIF0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .name = "hif0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .sta_mask = PWR_STATUS_HIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .ctl_offs = SPM_HIF0_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .clk_id = {CLK_HIFSEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) [MT7622_POWER_DOMAIN_HIF1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .name = "hif1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .sta_mask = PWR_STATUS_HIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .ctl_offs = SPM_HIF1_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .clk_id = {CLK_HIFSEL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) [MT7622_POWER_DOMAIN_WB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .name = "wb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .sta_mask = PWR_STATUS_WB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .ctl_offs = SPM_WB_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .sram_pdn_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .sram_pdn_ack_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * MT7623A power domain support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const struct scp_domain_data scp_domain_data_mt7623a[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) [MT7623A_POWER_DOMAIN_CONN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .name = "conn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .sta_mask = PWR_STATUS_CONN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .ctl_offs = SPM_CONN_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MT2701_TOP_AXI_PROT_EN_CONN_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) [MT7623A_POWER_DOMAIN_ETH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .name = "eth",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .sta_mask = PWR_STATUS_ETH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .ctl_offs = SPM_ETH_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .clk_id = {CLK_ETHIF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [MT7623A_POWER_DOMAIN_HIF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .name = "hif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .sta_mask = PWR_STATUS_HIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .ctl_offs = SPM_HIF_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .clk_id = {CLK_ETHIF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) [MT7623A_POWER_DOMAIN_IFR_MSC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .name = "ifr_msc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .sta_mask = PWR_STATUS_IFR_MSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .ctl_offs = SPM_IFR_MSC_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * MT8173 power domain support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const struct scp_domain_data scp_domain_data_mt8173[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) [MT8173_POWER_DOMAIN_VDEC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .name = "vdec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .sta_mask = PWR_STATUS_VDEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .ctl_offs = SPM_VDE_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .sram_pdn_ack_bits = GENMASK(12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .clk_id = {CLK_MM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) [MT8173_POWER_DOMAIN_VENC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .name = "venc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .sta_mask = PWR_STATUS_VENC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .ctl_offs = SPM_VEN_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .clk_id = {CLK_MM, CLK_VENC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) [MT8173_POWER_DOMAIN_ISP] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .name = "isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .sta_mask = PWR_STATUS_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .ctl_offs = SPM_ISP_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .sram_pdn_ack_bits = GENMASK(13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .clk_id = {CLK_MM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) [MT8173_POWER_DOMAIN_MM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .name = "mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .sta_mask = PWR_STATUS_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .ctl_offs = SPM_DIS_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .sram_pdn_ack_bits = GENMASK(12, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .clk_id = {CLK_MM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) MT8173_TOP_AXI_PROT_EN_MM_M1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) [MT8173_POWER_DOMAIN_VENC_LT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .name = "venc_lt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .sta_mask = PWR_STATUS_VENC_LT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .ctl_offs = SPM_VEN2_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .clk_id = {CLK_MM, CLK_VENC_LT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) [MT8173_POWER_DOMAIN_AUDIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .name = "audio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .sta_mask = PWR_STATUS_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .ctl_offs = SPM_AUDIO_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [MT8173_POWER_DOMAIN_USB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .name = "usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .sta_mask = PWR_STATUS_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .ctl_offs = SPM_USB_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .sram_pdn_ack_bits = GENMASK(15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .caps = MTK_SCPD_ACTIVE_WAKEUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .name = "mfg_async",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .sta_mask = PWR_STATUS_MFG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .sram_pdn_ack_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .clk_id = {CLK_MFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) [MT8173_POWER_DOMAIN_MFG_2D] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .name = "mfg_2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .sta_mask = PWR_STATUS_MFG_2D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .ctl_offs = SPM_MFG_2D_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .sram_pdn_bits = GENMASK(11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .sram_pdn_ack_bits = GENMASK(13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [MT8173_POWER_DOMAIN_MFG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .name = "mfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .sta_mask = PWR_STATUS_MFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .ctl_offs = SPM_MFG_PWR_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .sram_pdn_bits = GENMASK(13, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .sram_pdn_ack_bits = GENMASK(21, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .clk_id = {CLK_NONE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) MT8173_TOP_AXI_PROT_EN_MFG_M0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) MT8173_TOP_AXI_PROT_EN_MFG_M1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const struct scp_subdomain scp_subdomain_mt8173[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {MT8173_POWER_DOMAIN_MFG_ASYNC, MT8173_POWER_DOMAIN_MFG_2D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static const struct scp_soc_data mt2701_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .domains = scp_domain_data_mt2701,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .pwr_sta_offs = SPM_PWR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .bus_prot_reg_update = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static const struct scp_soc_data mt2712_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .domains = scp_domain_data_mt2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .num_domains = ARRAY_SIZE(scp_domain_data_mt2712),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .subdomains = scp_subdomain_mt2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .pwr_sta_offs = SPM_PWR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .bus_prot_reg_update = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const struct scp_soc_data mt6797_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .domains = scp_domain_data_mt6797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .subdomains = scp_subdomain_mt6797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6797),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .pwr_sta_offs = SPM_PWR_STATUS_MT6797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .bus_prot_reg_update = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct scp_soc_data mt7622_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .domains = scp_domain_data_mt7622,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .num_domains = ARRAY_SIZE(scp_domain_data_mt7622),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .pwr_sta_offs = SPM_PWR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .bus_prot_reg_update = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const struct scp_soc_data mt7623a_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .domains = scp_domain_data_mt7623a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .num_domains = ARRAY_SIZE(scp_domain_data_mt7623a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .pwr_sta_offs = SPM_PWR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .bus_prot_reg_update = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static const struct scp_soc_data mt8173_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .domains = scp_domain_data_mt8173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .num_domains = ARRAY_SIZE(scp_domain_data_mt8173),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .subdomains = scp_subdomain_mt8173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8173),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .pwr_sta_offs = SPM_PWR_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .bus_prot_reg_update = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * scpsys driver init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static const struct of_device_id of_scpsys_match_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .compatible = "mediatek,mt2701-scpsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .data = &mt2701_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .compatible = "mediatek,mt2712-scpsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .data = &mt2712_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .compatible = "mediatek,mt6797-scpsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .data = &mt6797_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .compatible = "mediatek,mt7622-scpsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .data = &mt7622_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .compatible = "mediatek,mt7623a-scpsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .data = &mt7623a_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .compatible = "mediatek,mt8173-scpsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .data = &mt8173_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static int scpsys_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) const struct scp_subdomain *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) const struct scp_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct scp *scp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct genpd_onecell_data *pd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) soc->bus_prot_reg_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (IS_ERR(scp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return PTR_ERR(scp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) mtk_register_power_domains(pdev, scp, soc->num_domains);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) pd_data = &scp->pd_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) pd_data->domains[sd->subdomain]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (ret && IS_ENABLED(CONFIG_PM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dev_err(&pdev->dev, "Failed to add subdomain: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static struct platform_driver scpsys_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .probe = scpsys_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .name = "mtk-scpsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .of_match_table = of_match_ptr(of_scpsys_match_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) builtin_platform_driver(scpsys_drv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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