^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Flora Fu, MediaTek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PWRAP_MT8135_BRIDGE_INT_EN 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* macro for wrapper status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PWRAP_STATE_INIT_DONE0 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* macro for WACS FSM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PWRAP_WACS_FSM_IDLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PWRAP_WACS_FSM_REQ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PWRAP_WACS_FSM_WFDLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PWRAP_WACS_FSM_WFVLDCLR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PWRAP_WACS_INIT_DONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PWRAP_WACS_WACS_SYNC_IDLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PWRAP_WACS_SYNC_BUSY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* macro for device wrapper default value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PWRAP_DEW_READ_TEST_VAL 0x5aa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* macro for manual command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* macro for Watch Dog Timer Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Group of bits used for shown slave capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PWRAP_SLV_CAP_SPI BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PWRAP_SLV_CAP_DUALIO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PWRAP_SLV_CAP_SECURITY BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Group of bits used for shown pwrap capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PWRAP_CAP_BRIDGE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PWRAP_CAP_RESET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PWRAP_CAP_DCM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PWRAP_CAP_INT1_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PWRAP_CAP_WDT_SRC1 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* defines for slave device wrapper registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) enum dew_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PWRAP_DEW_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PWRAP_DEW_DIO_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PWRAP_DEW_READ_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PWRAP_DEW_WRITE_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PWRAP_DEW_CRC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PWRAP_DEW_CRC_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PWRAP_DEW_MON_GRP_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PWRAP_DEW_CIPHER_KEY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PWRAP_DEW_CIPHER_IV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PWRAP_DEW_CIPHER_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PWRAP_DEW_CIPHER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PWRAP_DEW_CIPHER_SWRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* MT6323 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PWRAP_DEW_CIPHER_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PWRAP_DEW_RDDMY_NO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* MT6358 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PWRAP_SMT_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PWRAP_DRV_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PWRAP_FILTER_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PWRAP_GPIO_PULLEN0_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PWRAP_RG_SPI_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PWRAP_RG_SPI_RECORD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PWRAP_RG_SPI_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PWRAP_RG_SPI_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PWRAP_RG_SPI_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PWRAP_RG_SPI_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PWRAP_RG_SPI_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PWRAP_RG_SPI_CON7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PWRAP_RG_SPI_CON8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PWRAP_RG_SPI_CON13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PWRAP_SPISLV_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* MT6359 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PWRAP_DEW_CRC_SWRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PWRAP_DEW_RG_EN_RECORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PWRAP_DEW_RECORD_CMD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PWRAP_DEW_RECORD_CMD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PWRAP_DEW_RECORD_CMD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PWRAP_DEW_RECORD_CMD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PWRAP_DEW_RECORD_CMD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PWRAP_DEW_RECORD_CMD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PWRAP_DEW_RECORD_WDATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PWRAP_DEW_RECORD_WDATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PWRAP_DEW_RECORD_WDATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PWRAP_DEW_RECORD_WDATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PWRAP_DEW_RECORD_WDATA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PWRAP_DEW_RECORD_WDATA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PWRAP_DEW_RG_ADDR_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PWRAP_DEW_RG_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PWRAP_DEW_RG_WDATA_TARGET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PWRAP_DEW_RG_WDATA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PWRAP_DEW_RG_SPI_RECORD_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PWRAP_DEW_RG_CMD_ALERT_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* MT6397 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PWRAP_DEW_EVENT_OUT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PWRAP_DEW_EVENT_SRC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PWRAP_DEW_EVENT_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PWRAP_DEW_EVENT_FLAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PWRAP_DEW_MON_FLAG_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PWRAP_DEW_EVENT_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PWRAP_DEW_CIPHER_LOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PWRAP_DEW_CIPHER_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const u32 mt6323_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [PWRAP_DEW_BASE] = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [PWRAP_DEW_DIO_EN] = 0x018a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [PWRAP_DEW_READ_TEST] = 0x018c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [PWRAP_DEW_WRITE_TEST] = 0x018e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [PWRAP_DEW_CRC_EN] = 0x0192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [PWRAP_DEW_CRC_VAL] = 0x0194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [PWRAP_DEW_MON_GRP_SEL] = 0x0196,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [PWRAP_DEW_CIPHER_EN] = 0x019c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [PWRAP_DEW_CIPHER_RDY] = 0x019e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [PWRAP_DEW_CIPHER_MODE] = 0x01a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [PWRAP_DEW_RDDMY_NO] = 0x01a4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const u32 mt6351_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [PWRAP_DEW_DIO_EN] = 0x02F2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [PWRAP_DEW_READ_TEST] = 0x02F4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [PWRAP_DEW_WRITE_TEST] = 0x02F6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [PWRAP_DEW_CRC_EN] = 0x02FA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [PWRAP_DEW_CRC_VAL] = 0x02FC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [PWRAP_DEW_CIPHER_EN] = 0x0304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) [PWRAP_DEW_CIPHER_RDY] = 0x0306,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [PWRAP_DEW_CIPHER_MODE] = 0x0308,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [PWRAP_DEW_CIPHER_SWRST] = 0x030A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [PWRAP_DEW_RDDMY_NO] = 0x030C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const u32 mt6357_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [PWRAP_DEW_DIO_EN] = 0x040A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [PWRAP_DEW_READ_TEST] = 0x040C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [PWRAP_DEW_WRITE_TEST] = 0x040E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) [PWRAP_DEW_CRC_EN] = 0x0412,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [PWRAP_DEW_CRC_VAL] = 0x0414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [PWRAP_DEW_CIPHER_IV_SEL] = 0x041A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [PWRAP_DEW_CIPHER_EN] = 0x041C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [PWRAP_DEW_CIPHER_RDY] = 0x041E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [PWRAP_DEW_CIPHER_MODE] = 0x0420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [PWRAP_DEW_RDDMY_NO] = 0x0424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const u32 mt6358_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [PWRAP_SMT_CON1] = 0x0030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [PWRAP_DRV_CON1] = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) [PWRAP_FILTER_CON0] = 0x0040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [PWRAP_GPIO_PULLEN0_CLR] = 0x0098,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [PWRAP_RG_SPI_CON0] = 0x0408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [PWRAP_RG_SPI_RECORD0] = 0x040a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [PWRAP_DEW_DIO_EN] = 0x040c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) [PWRAP_DEW_READ_TEST] = 0x040e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [PWRAP_DEW_WRITE_TEST] = 0x0410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [PWRAP_DEW_CRC_EN] = 0x0414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [PWRAP_DEW_CIPHER_KEY_SEL] = 0x041a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [PWRAP_DEW_CIPHER_EN] = 0x041e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [PWRAP_DEW_CIPHER_RDY] = 0x0420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [PWRAP_DEW_CIPHER_MODE] = 0x0422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [PWRAP_DEW_CIPHER_SWRST] = 0x0424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [PWRAP_RG_SPI_CON2] = 0x0432,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [PWRAP_RG_SPI_CON3] = 0x0434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) [PWRAP_RG_SPI_CON4] = 0x0436,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [PWRAP_RG_SPI_CON5] = 0x0438,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [PWRAP_RG_SPI_CON6] = 0x043a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [PWRAP_RG_SPI_CON7] = 0x043c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [PWRAP_RG_SPI_CON8] = 0x043e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [PWRAP_RG_SPI_CON13] = 0x0448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [PWRAP_SPISLV_KEY] = 0x044a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const u32 mt6359_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) [PWRAP_DEW_RG_EN_RECORD] = 0x040a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [PWRAP_DEW_DIO_EN] = 0x040c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [PWRAP_DEW_READ_TEST] = 0x040e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [PWRAP_DEW_WRITE_TEST] = 0x0410,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [PWRAP_DEW_CRC_SWRST] = 0x0412,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [PWRAP_DEW_CRC_EN] = 0x0414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [PWRAP_DEW_CRC_VAL] = 0x0416,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [PWRAP_DEW_CIPHER_EN] = 0x041c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) [PWRAP_DEW_CIPHER_RDY] = 0x041e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) [PWRAP_DEW_CIPHER_MODE] = 0x0420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [PWRAP_DEW_CIPHER_SWRST] = 0x0422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [PWRAP_DEW_RDDMY_NO] = 0x0424,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [PWRAP_DEW_RECORD_CMD0] = 0x0428,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [PWRAP_DEW_RECORD_CMD1] = 0x042a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [PWRAP_DEW_RECORD_CMD2] = 0x042c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [PWRAP_DEW_RECORD_CMD3] = 0x042e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [PWRAP_DEW_RECORD_CMD4] = 0x0430,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) [PWRAP_DEW_RECORD_CMD5] = 0x0432,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [PWRAP_DEW_RECORD_WDATA0] = 0x0434,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [PWRAP_DEW_RECORD_WDATA1] = 0x0436,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [PWRAP_DEW_RECORD_WDATA2] = 0x0438,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [PWRAP_DEW_RECORD_WDATA3] = 0x043a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [PWRAP_DEW_RECORD_WDATA4] = 0x043c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) [PWRAP_DEW_RECORD_WDATA5] = 0x043e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) [PWRAP_DEW_RG_ADDR_TARGET] = 0x0440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [PWRAP_DEW_RG_ADDR_MASK] = 0x0442,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) [PWRAP_DEW_RG_WDATA_TARGET] = 0x0444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) [PWRAP_DEW_RG_WDATA_MASK] = 0x0446,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) [PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [PWRAP_SPISLV_KEY] = 0x044a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const u32 mt6397_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [PWRAP_DEW_BASE] = 0xbc00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [PWRAP_DEW_DIO_EN] = 0xbc02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [PWRAP_DEW_EVENT_SRC] = 0xbc06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [PWRAP_DEW_READ_TEST] = 0xbc0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) [PWRAP_DEW_CRC_EN] = 0xbc0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [PWRAP_DEW_CRC_VAL] = 0xbc10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [PWRAP_DEW_EVENT_TEST] = 0xbc16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [PWRAP_DEW_CIPHER_START] = 0xbc1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) enum pwrap_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PWRAP_MUX_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PWRAP_WRAP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PWRAP_DIO_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PWRAP_SIDLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PWRAP_CSHEXT_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PWRAP_CSHEXT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PWRAP_CSLEXT_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PWRAP_CSLEXT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PWRAP_STAUPD_PRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PWRAP_STAUPD_GRPEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PWRAP_STAUPD_MAN_TRIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PWRAP_STAUPD_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PWRAP_WRAP_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PWRAP_HARB_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PWRAP_HARB_HPRIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PWRAP_HIPRIO_ARB_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PWRAP_HARB_STA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PWRAP_HARB_STA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PWRAP_MAN_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PWRAP_MAN_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PWRAP_MAN_RDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PWRAP_MAN_VLDCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PWRAP_WACS0_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PWRAP_INIT_DONE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PWRAP_WACS0_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PWRAP_WACS0_RDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PWRAP_WACS0_VLDCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PWRAP_WACS1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PWRAP_INIT_DONE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PWRAP_WACS1_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PWRAP_WACS1_RDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PWRAP_WACS1_VLDCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PWRAP_WACS2_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PWRAP_INIT_DONE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PWRAP_WACS2_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PWRAP_WACS2_RDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PWRAP_WACS2_VLDCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PWRAP_INT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PWRAP_INT_FLG_RAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PWRAP_INT_FLG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PWRAP_INT_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PWRAP_SIG_ADR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PWRAP_SIG_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PWRAP_SIG_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PWRAP_SIG_ERRVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PWRAP_CRC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PWRAP_TIMER_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PWRAP_TIMER_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PWRAP_WDT_UNIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PWRAP_WDT_SRC_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PWRAP_WDT_FLG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PWRAP_DEBUG_INT_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PWRAP_CIPHER_KEY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PWRAP_CIPHER_IV_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PWRAP_CIPHER_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PWRAP_CIPHER_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PWRAP_CIPHER_SWRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PWRAP_DCM_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PWRAP_DCM_DBC_PRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PWRAP_EINT_STA0_ADR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PWRAP_EINT_STA1_ADR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* MT2701 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PWRAP_ADC_CMD_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PWRAP_PWRAP_ADC_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PWRAP_ADC_RDY_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PWRAP_ADC_RDATA_ADDR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PWRAP_ADC_RDATA_ADDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* MT7622 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PWRAP_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PWRAP_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PWRAP_DVFS_ADR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PWRAP_DVFS_WDATA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PWRAP_DVFS_ADR9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PWRAP_DVFS_WDATA9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PWRAP_DVFS_ADR10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PWRAP_DVFS_WDATA10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PWRAP_DVFS_ADR11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PWRAP_DVFS_WDATA11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PWRAP_DVFS_ADR12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PWRAP_DVFS_WDATA12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PWRAP_DVFS_ADR13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PWRAP_DVFS_WDATA13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PWRAP_DVFS_ADR14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PWRAP_DVFS_WDATA14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PWRAP_DVFS_ADR15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PWRAP_DVFS_WDATA15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PWRAP_EXT_CK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PWRAP_ADC_RDATA_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PWRAP_GPS_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PWRAP_SW_RST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PWRAP_DVFS_STEP_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PWRAP_DVFS_STEP_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PWRAP_DVFS_STEP_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PWRAP_SPI2_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* MT8135 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PWRAP_CSHEXT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PWRAP_EVENT_IN_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PWRAP_EVENT_DST_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PWRAP_RRARB_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PWRAP_RRARB_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PWRAP_RRARB_STA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PWRAP_RRARB_STA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PWRAP_EVENT_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PWRAP_EVENT_STACLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PWRAP_CIPHER_LOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PWRAP_CIPHER_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* MT8173 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PWRAP_RDDMY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PWRAP_SI_CK_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PWRAP_DVFS_ADR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PWRAP_DVFS_WDATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PWRAP_DVFS_ADR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PWRAP_DVFS_WDATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PWRAP_DVFS_ADR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PWRAP_DVFS_WDATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PWRAP_DVFS_ADR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PWRAP_DVFS_WDATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PWRAP_DVFS_ADR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PWRAP_DVFS_WDATA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PWRAP_DVFS_ADR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PWRAP_DVFS_WDATA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PWRAP_DVFS_ADR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PWRAP_DVFS_WDATA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PWRAP_DVFS_ADR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PWRAP_DVFS_WDATA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PWRAP_SPMINF_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PWRAP_CIPHER_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* MT8183 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PWRAP_SI_SAMPLE_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PWRAP_CSLEXT_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PWRAP_CSLEXT_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PWRAP_EXT_CK_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PWRAP_STAUPD_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PWRAP_WACS_P2P_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PWRAP_INIT_DONE_P2P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PWRAP_WACS_MD32_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PWRAP_INIT_DONE_MD32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PWRAP_INT1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PWRAP_INT1_FLG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PWRAP_INT1_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PWRAP_WDT_SRC_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PWRAP_INT_GPS_AUXADC_CMD_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PWRAP_INT_GPS_AUXADC_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PWRAP_GPSINF_0_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PWRAP_GPSINF_1_STA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* MT8516 only regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PWRAP_OP_TYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PWRAP_MSB_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int mt2701_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [PWRAP_MUX_SEL] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) [PWRAP_WRAP_EN] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [PWRAP_DIO_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [PWRAP_SIDLY] = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [PWRAP_RDDMY] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [PWRAP_SI_CK_CON] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) [PWRAP_CSHEXT_WRITE] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [PWRAP_CSHEXT_READ] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) [PWRAP_CSLEXT_START] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) [PWRAP_CSLEXT_END] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [PWRAP_STAUPD_PRD] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) [PWRAP_STAUPD_GRPEN] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) [PWRAP_STAUPD_MAN_TRIG] = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) [PWRAP_STAUPD_STA] = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) [PWRAP_WRAP_STA] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) [PWRAP_HARB_INIT] = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) [PWRAP_HARB_HPRIO] = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) [PWRAP_HIPRIO_ARB_EN] = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) [PWRAP_HARB_STA0] = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) [PWRAP_HARB_STA1] = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [PWRAP_MAN_EN] = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) [PWRAP_MAN_CMD] = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) [PWRAP_MAN_RDATA] = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) [PWRAP_MAN_VLDCLR] = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) [PWRAP_WACS0_EN] = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) [PWRAP_INIT_DONE0] = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) [PWRAP_WACS0_CMD] = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) [PWRAP_WACS0_RDATA] = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) [PWRAP_WACS0_VLDCLR] = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [PWRAP_WACS1_EN] = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [PWRAP_INIT_DONE1] = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) [PWRAP_WACS1_CMD] = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [PWRAP_WACS1_RDATA] = 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) [PWRAP_WACS1_VLDCLR] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [PWRAP_WACS2_EN] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) [PWRAP_INIT_DONE2] = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) [PWRAP_WACS2_CMD] = 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) [PWRAP_WACS2_RDATA] = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [PWRAP_WACS2_VLDCLR] = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) [PWRAP_INT_EN] = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) [PWRAP_INT_FLG_RAW] = 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) [PWRAP_INT_FLG] = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) [PWRAP_INT_CLR] = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) [PWRAP_SIG_ADR] = 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [PWRAP_SIG_MODE] = 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) [PWRAP_SIG_VALUE] = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [PWRAP_SIG_ERRVAL] = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [PWRAP_CRC_EN] = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [PWRAP_TIMER_EN] = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) [PWRAP_TIMER_STA] = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [PWRAP_WDT_UNIT] = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [PWRAP_WDT_SRC_EN] = 0xd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [PWRAP_WDT_FLG] = 0xdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [PWRAP_DEBUG_INT_SEL] = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [PWRAP_DVFS_ADR0] = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [PWRAP_DVFS_WDATA0] = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [PWRAP_DVFS_ADR1] = 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [PWRAP_DVFS_WDATA1] = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) [PWRAP_DVFS_ADR2] = 0xf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) [PWRAP_DVFS_WDATA2] = 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) [PWRAP_DVFS_ADR3] = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) [PWRAP_DVFS_WDATA3] = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) [PWRAP_DVFS_ADR4] = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) [PWRAP_DVFS_WDATA4] = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) [PWRAP_DVFS_ADR5] = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) [PWRAP_DVFS_WDATA5] = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) [PWRAP_DVFS_ADR6] = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [PWRAP_DVFS_WDATA6] = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [PWRAP_DVFS_ADR7] = 0x11c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) [PWRAP_DVFS_WDATA7] = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) [PWRAP_CIPHER_KEY_SEL] = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) [PWRAP_CIPHER_IV_SEL] = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) [PWRAP_CIPHER_EN] = 0x12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) [PWRAP_CIPHER_RDY] = 0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) [PWRAP_CIPHER_MODE] = 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [PWRAP_CIPHER_SWRST] = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [PWRAP_DCM_EN] = 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) [PWRAP_DCM_DBC_PRD] = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) [PWRAP_ADC_CMD_ADDR] = 0x144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) [PWRAP_PWRAP_ADC_CMD] = 0x148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) [PWRAP_ADC_RDY_ADDR] = 0x14c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) [PWRAP_ADC_RDATA_ADDR1] = 0x150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) [PWRAP_ADC_RDATA_ADDR2] = 0x154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int mt6765_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) [PWRAP_MUX_SEL] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) [PWRAP_WRAP_EN] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) [PWRAP_DIO_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) [PWRAP_RDDMY] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) [PWRAP_CSHEXT_WRITE] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) [PWRAP_CSHEXT_READ] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) [PWRAP_CSLEXT_START] = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) [PWRAP_CSLEXT_END] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) [PWRAP_STAUPD_PRD] = 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) [PWRAP_HARB_HPRIO] = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) [PWRAP_HIPRIO_ARB_EN] = 0x6C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) [PWRAP_MAN_EN] = 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) [PWRAP_MAN_CMD] = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) [PWRAP_WACS0_EN] = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) [PWRAP_WACS1_EN] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) [PWRAP_WACS2_EN] = 0x9C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) [PWRAP_INIT_DONE2] = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) [PWRAP_WACS2_CMD] = 0xC20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) [PWRAP_WACS2_RDATA] = 0xC24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) [PWRAP_WACS2_VLDCLR] = 0xC28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) [PWRAP_INT_EN] = 0xB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) [PWRAP_INT_FLG_RAW] = 0xB8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) [PWRAP_INT_FLG] = 0xBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) [PWRAP_INT_CLR] = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [PWRAP_TIMER_EN] = 0xE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) [PWRAP_WDT_UNIT] = 0xF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [PWRAP_WDT_SRC_EN] = 0xF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) [PWRAP_DCM_EN] = 0x1DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) [PWRAP_DCM_DBC_PRD] = 0x1E0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int mt6779_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) [PWRAP_MUX_SEL] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) [PWRAP_WRAP_EN] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) [PWRAP_DIO_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) [PWRAP_RDDMY] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) [PWRAP_CSHEXT_WRITE] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) [PWRAP_CSHEXT_READ] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) [PWRAP_CSLEXT_WRITE] = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) [PWRAP_CSLEXT_READ] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [PWRAP_EXT_CK_WRITE] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) [PWRAP_STAUPD_CTRL] = 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) [PWRAP_STAUPD_GRPEN] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) [PWRAP_EINT_STA0_ADR] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) [PWRAP_HARB_HPRIO] = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) [PWRAP_HIPRIO_ARB_EN] = 0x6C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) [PWRAP_MAN_EN] = 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) [PWRAP_MAN_CMD] = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) [PWRAP_WACS0_EN] = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) [PWRAP_INIT_DONE0] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) [PWRAP_WACS1_EN] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) [PWRAP_WACS2_EN] = 0x9C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) [PWRAP_INIT_DONE1] = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) [PWRAP_INIT_DONE2] = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) [PWRAP_INT_EN] = 0xBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) [PWRAP_INT_FLG_RAW] = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) [PWRAP_INT_FLG] = 0xC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) [PWRAP_INT_CLR] = 0xC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) [PWRAP_INT1_EN] = 0xCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) [PWRAP_INT1_FLG] = 0xD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) [PWRAP_INT1_CLR] = 0xD8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) [PWRAP_TIMER_EN] = 0xF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) [PWRAP_WDT_UNIT] = 0xF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) [PWRAP_WDT_SRC_EN] = 0xFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) [PWRAP_WDT_SRC_EN_1] = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) [PWRAP_WACS2_CMD] = 0xC20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) [PWRAP_WACS2_RDATA] = 0xC24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) [PWRAP_WACS2_VLDCLR] = 0xC28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int mt6797_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) [PWRAP_MUX_SEL] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) [PWRAP_WRAP_EN] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) [PWRAP_DIO_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) [PWRAP_SIDLY] = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) [PWRAP_RDDMY] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) [PWRAP_CSHEXT_WRITE] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) [PWRAP_CSHEXT_READ] = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) [PWRAP_CSLEXT_START] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) [PWRAP_CSLEXT_END] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) [PWRAP_STAUPD_PRD] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) [PWRAP_HARB_HPRIO] = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) [PWRAP_HIPRIO_ARB_EN] = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) [PWRAP_MAN_EN] = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) [PWRAP_MAN_CMD] = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) [PWRAP_WACS0_EN] = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) [PWRAP_WACS1_EN] = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) [PWRAP_WACS2_EN] = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) [PWRAP_INIT_DONE2] = 0x9C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) [PWRAP_WACS2_CMD] = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) [PWRAP_WACS2_RDATA] = 0xA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) [PWRAP_WACS2_VLDCLR] = 0xA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) [PWRAP_INT_EN] = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) [PWRAP_INT_FLG_RAW] = 0xC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) [PWRAP_INT_FLG] = 0xC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) [PWRAP_INT_CLR] = 0xCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) [PWRAP_TIMER_EN] = 0xF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) [PWRAP_WDT_UNIT] = 0xFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) [PWRAP_WDT_SRC_EN] = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) [PWRAP_DCM_EN] = 0x1CC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) [PWRAP_DCM_DBC_PRD] = 0x1D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int mt7622_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) [PWRAP_MUX_SEL] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) [PWRAP_WRAP_EN] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) [PWRAP_DIO_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) [PWRAP_SIDLY] = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) [PWRAP_RDDMY] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) [PWRAP_SI_CK_CON] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) [PWRAP_CSHEXT_WRITE] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) [PWRAP_CSHEXT_READ] = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) [PWRAP_CSLEXT_START] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) [PWRAP_CSLEXT_END] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) [PWRAP_STAUPD_PRD] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) [PWRAP_STAUPD_GRPEN] = 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) [PWRAP_EINT_STA0_ADR] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) [PWRAP_EINT_STA1_ADR] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) [PWRAP_STA] = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) [PWRAP_CLR] = 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) [PWRAP_STAUPD_MAN_TRIG] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) [PWRAP_STAUPD_STA] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) [PWRAP_WRAP_STA] = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) [PWRAP_HARB_INIT] = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) [PWRAP_HARB_HPRIO] = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) [PWRAP_HIPRIO_ARB_EN] = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) [PWRAP_HARB_STA0] = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) [PWRAP_HARB_STA1] = 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) [PWRAP_MAN_EN] = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) [PWRAP_MAN_CMD] = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) [PWRAP_MAN_RDATA] = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) [PWRAP_MAN_VLDCLR] = 0x6C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) [PWRAP_WACS0_EN] = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) [PWRAP_INIT_DONE0] = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) [PWRAP_WACS0_CMD] = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [PWRAP_WACS0_RDATA] = 0x7C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) [PWRAP_WACS0_VLDCLR] = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) [PWRAP_WACS1_EN] = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) [PWRAP_INIT_DONE1] = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) [PWRAP_WACS1_CMD] = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) [PWRAP_WACS1_RDATA] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) [PWRAP_WACS1_VLDCLR] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) [PWRAP_WACS2_EN] = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) [PWRAP_INIT_DONE2] = 0x9C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) [PWRAP_WACS2_CMD] = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) [PWRAP_WACS2_RDATA] = 0xA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) [PWRAP_WACS2_VLDCLR] = 0xA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) [PWRAP_INT_EN] = 0xAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) [PWRAP_INT_FLG_RAW] = 0xB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) [PWRAP_INT_FLG] = 0xB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) [PWRAP_INT_CLR] = 0xB8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) [PWRAP_SIG_ADR] = 0xBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) [PWRAP_SIG_MODE] = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) [PWRAP_SIG_VALUE] = 0xC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) [PWRAP_SIG_ERRVAL] = 0xC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) [PWRAP_CRC_EN] = 0xCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) [PWRAP_TIMER_EN] = 0xD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) [PWRAP_TIMER_STA] = 0xD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) [PWRAP_WDT_UNIT] = 0xD8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) [PWRAP_WDT_SRC_EN] = 0xDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [PWRAP_WDT_FLG] = 0xE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) [PWRAP_DEBUG_INT_SEL] = 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) [PWRAP_DVFS_ADR0] = 0xE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) [PWRAP_DVFS_WDATA0] = 0xEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [PWRAP_DVFS_ADR1] = 0xF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) [PWRAP_DVFS_WDATA1] = 0xF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [PWRAP_DVFS_ADR2] = 0xF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) [PWRAP_DVFS_WDATA2] = 0xFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [PWRAP_DVFS_ADR3] = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [PWRAP_DVFS_WDATA3] = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [PWRAP_DVFS_ADR4] = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [PWRAP_DVFS_WDATA4] = 0x10C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) [PWRAP_DVFS_ADR5] = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [PWRAP_DVFS_WDATA5] = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [PWRAP_DVFS_ADR6] = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) [PWRAP_DVFS_WDATA6] = 0x11C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) [PWRAP_DVFS_ADR7] = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [PWRAP_DVFS_WDATA7] = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [PWRAP_DVFS_ADR8] = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) [PWRAP_DVFS_WDATA8] = 0x12C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [PWRAP_DVFS_ADR9] = 0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) [PWRAP_DVFS_WDATA9] = 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [PWRAP_DVFS_ADR10] = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) [PWRAP_DVFS_WDATA10] = 0x13C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) [PWRAP_DVFS_ADR11] = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) [PWRAP_DVFS_WDATA11] = 0x144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) [PWRAP_DVFS_ADR12] = 0x148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) [PWRAP_DVFS_WDATA12] = 0x14C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) [PWRAP_DVFS_ADR13] = 0x150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) [PWRAP_DVFS_WDATA13] = 0x154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) [PWRAP_DVFS_ADR14] = 0x158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) [PWRAP_DVFS_WDATA14] = 0x15C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) [PWRAP_DVFS_ADR15] = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) [PWRAP_DVFS_WDATA15] = 0x164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) [PWRAP_SPMINF_STA] = 0x168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) [PWRAP_CIPHER_KEY_SEL] = 0x16C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) [PWRAP_CIPHER_IV_SEL] = 0x170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) [PWRAP_CIPHER_EN] = 0x174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) [PWRAP_CIPHER_RDY] = 0x178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) [PWRAP_CIPHER_MODE] = 0x17C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) [PWRAP_CIPHER_SWRST] = 0x180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) [PWRAP_DCM_EN] = 0x184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) [PWRAP_DCM_DBC_PRD] = 0x188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) [PWRAP_EXT_CK] = 0x18C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) [PWRAP_ADC_CMD_ADDR] = 0x190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) [PWRAP_PWRAP_ADC_CMD] = 0x194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) [PWRAP_ADC_RDATA_ADDR] = 0x198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) [PWRAP_GPS_STA] = 0x19C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) [PWRAP_SW_RST] = 0x1A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) [PWRAP_DVFS_STEP_CTRL0] = 0x238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) [PWRAP_DVFS_STEP_CTRL1] = 0x23C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) [PWRAP_DVFS_STEP_CTRL2] = 0x240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) [PWRAP_SPI2_CTRL] = 0x244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int mt8135_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) [PWRAP_MUX_SEL] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) [PWRAP_WRAP_EN] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) [PWRAP_DIO_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) [PWRAP_SIDLY] = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) [PWRAP_CSHEXT] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) [PWRAP_CSHEXT_WRITE] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) [PWRAP_CSHEXT_READ] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) [PWRAP_CSLEXT_START] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) [PWRAP_CSLEXT_END] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) [PWRAP_STAUPD_PRD] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) [PWRAP_STAUPD_GRPEN] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) [PWRAP_STAUPD_STA] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [PWRAP_EVENT_IN_EN] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) [PWRAP_EVENT_DST_EN] = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) [PWRAP_WRAP_STA] = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) [PWRAP_RRARB_INIT] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) [PWRAP_RRARB_EN] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) [PWRAP_RRARB_STA0] = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) [PWRAP_RRARB_STA1] = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) [PWRAP_HARB_INIT] = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [PWRAP_HARB_HPRIO] = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) [PWRAP_HIPRIO_ARB_EN] = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) [PWRAP_HARB_STA0] = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) [PWRAP_HARB_STA1] = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) [PWRAP_MAN_EN] = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) [PWRAP_MAN_CMD] = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) [PWRAP_MAN_RDATA] = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) [PWRAP_MAN_VLDCLR] = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) [PWRAP_WACS0_EN] = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [PWRAP_INIT_DONE0] = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [PWRAP_WACS0_CMD] = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) [PWRAP_WACS0_RDATA] = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) [PWRAP_WACS0_VLDCLR] = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) [PWRAP_WACS1_EN] = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [PWRAP_INIT_DONE1] = 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) [PWRAP_WACS1_CMD] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) [PWRAP_WACS1_RDATA] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) [PWRAP_WACS1_VLDCLR] = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) [PWRAP_WACS2_EN] = 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) [PWRAP_INIT_DONE2] = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) [PWRAP_WACS2_CMD] = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) [PWRAP_WACS2_RDATA] = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) [PWRAP_WACS2_VLDCLR] = 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) [PWRAP_INT_EN] = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) [PWRAP_INT_FLG_RAW] = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) [PWRAP_INT_FLG] = 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) [PWRAP_INT_CLR] = 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) [PWRAP_SIG_ADR] = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) [PWRAP_SIG_MODE] = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) [PWRAP_SIG_VALUE] = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) [PWRAP_SIG_ERRVAL] = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) [PWRAP_CRC_EN] = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) [PWRAP_EVENT_STA] = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) [PWRAP_EVENT_STACLR] = 0xd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) [PWRAP_TIMER_EN] = 0xdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) [PWRAP_TIMER_STA] = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) [PWRAP_WDT_UNIT] = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) [PWRAP_WDT_SRC_EN] = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) [PWRAP_WDT_FLG] = 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) [PWRAP_DEBUG_INT_SEL] = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) [PWRAP_CIPHER_KEY_SEL] = 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) [PWRAP_CIPHER_IV_SEL] = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) [PWRAP_CIPHER_LOAD] = 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) [PWRAP_CIPHER_START] = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) [PWRAP_CIPHER_RDY] = 0x144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) [PWRAP_CIPHER_MODE] = 0x148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) [PWRAP_CIPHER_SWRST] = 0x14c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) [PWRAP_DCM_EN] = 0x15c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) [PWRAP_DCM_DBC_PRD] = 0x160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int mt8173_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) [PWRAP_MUX_SEL] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) [PWRAP_WRAP_EN] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) [PWRAP_DIO_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) [PWRAP_SIDLY] = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) [PWRAP_RDDMY] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) [PWRAP_SI_CK_CON] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) [PWRAP_CSHEXT_WRITE] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) [PWRAP_CSHEXT_READ] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) [PWRAP_CSLEXT_START] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) [PWRAP_CSLEXT_END] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) [PWRAP_STAUPD_PRD] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) [PWRAP_STAUPD_GRPEN] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) [PWRAP_STAUPD_MAN_TRIG] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) [PWRAP_STAUPD_STA] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) [PWRAP_WRAP_STA] = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) [PWRAP_HARB_INIT] = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) [PWRAP_HARB_HPRIO] = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) [PWRAP_HIPRIO_ARB_EN] = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) [PWRAP_HARB_STA0] = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) [PWRAP_HARB_STA1] = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) [PWRAP_MAN_EN] = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) [PWRAP_MAN_CMD] = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) [PWRAP_MAN_RDATA] = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) [PWRAP_MAN_VLDCLR] = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) [PWRAP_WACS0_EN] = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) [PWRAP_INIT_DONE0] = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) [PWRAP_WACS0_CMD] = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) [PWRAP_WACS0_RDATA] = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) [PWRAP_WACS0_VLDCLR] = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) [PWRAP_WACS1_EN] = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) [PWRAP_INIT_DONE1] = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) [PWRAP_WACS1_CMD] = 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) [PWRAP_WACS1_RDATA] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) [PWRAP_WACS1_VLDCLR] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) [PWRAP_WACS2_EN] = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) [PWRAP_INIT_DONE2] = 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) [PWRAP_WACS2_CMD] = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) [PWRAP_WACS2_RDATA] = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) [PWRAP_WACS2_VLDCLR] = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) [PWRAP_INT_EN] = 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) [PWRAP_INT_FLG_RAW] = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) [PWRAP_INT_FLG] = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) [PWRAP_INT_CLR] = 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) [PWRAP_SIG_ADR] = 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) [PWRAP_SIG_MODE] = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) [PWRAP_SIG_VALUE] = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) [PWRAP_SIG_ERRVAL] = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) [PWRAP_CRC_EN] = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) [PWRAP_TIMER_EN] = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) [PWRAP_TIMER_STA] = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) [PWRAP_WDT_UNIT] = 0xd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) [PWRAP_WDT_SRC_EN] = 0xdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) [PWRAP_WDT_FLG] = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) [PWRAP_DEBUG_INT_SEL] = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) [PWRAP_DVFS_ADR0] = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) [PWRAP_DVFS_WDATA0] = 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) [PWRAP_DVFS_ADR1] = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) [PWRAP_DVFS_WDATA1] = 0xf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) [PWRAP_DVFS_ADR2] = 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) [PWRAP_DVFS_WDATA2] = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) [PWRAP_DVFS_ADR3] = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) [PWRAP_DVFS_WDATA3] = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) [PWRAP_DVFS_ADR4] = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) [PWRAP_DVFS_WDATA4] = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) [PWRAP_DVFS_ADR5] = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) [PWRAP_DVFS_WDATA5] = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) [PWRAP_DVFS_ADR6] = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) [PWRAP_DVFS_WDATA6] = 0x11c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) [PWRAP_DVFS_ADR7] = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) [PWRAP_DVFS_WDATA7] = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) [PWRAP_SPMINF_STA] = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) [PWRAP_CIPHER_KEY_SEL] = 0x12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) [PWRAP_CIPHER_IV_SEL] = 0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) [PWRAP_CIPHER_EN] = 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) [PWRAP_CIPHER_RDY] = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) [PWRAP_CIPHER_MODE] = 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) [PWRAP_CIPHER_SWRST] = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) [PWRAP_DCM_EN] = 0x144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) [PWRAP_DCM_DBC_PRD] = 0x148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int mt8183_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) [PWRAP_MUX_SEL] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) [PWRAP_WRAP_EN] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) [PWRAP_DIO_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) [PWRAP_SI_SAMPLE_CTRL] = 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) [PWRAP_RDDMY] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) [PWRAP_CSHEXT_WRITE] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) [PWRAP_CSHEXT_READ] = 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) [PWRAP_CSLEXT_WRITE] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) [PWRAP_CSLEXT_READ] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) [PWRAP_EXT_CK_WRITE] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) [PWRAP_STAUPD_CTRL] = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) [PWRAP_STAUPD_GRPEN] = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) [PWRAP_EINT_STA0_ADR] = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) [PWRAP_HARB_HPRIO] = 0x5C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) [PWRAP_HIPRIO_ARB_EN] = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) [PWRAP_MAN_EN] = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) [PWRAP_MAN_CMD] = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) [PWRAP_WACS0_EN] = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) [PWRAP_INIT_DONE0] = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) [PWRAP_WACS1_EN] = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) [PWRAP_INIT_DONE1] = 0x8C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) [PWRAP_WACS2_EN] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) [PWRAP_INIT_DONE2] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) [PWRAP_WACS_P2P_EN] = 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) [PWRAP_INIT_DONE_P2P] = 0xA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) [PWRAP_WACS_MD32_EN] = 0xA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) [PWRAP_INIT_DONE_MD32] = 0xAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) [PWRAP_INT_EN] = 0xB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) [PWRAP_INT_FLG] = 0xB8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) [PWRAP_INT_CLR] = 0xBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) [PWRAP_INT1_EN] = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) [PWRAP_INT1_FLG] = 0xC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) [PWRAP_INT1_CLR] = 0xCC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) [PWRAP_SIG_ADR] = 0xD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) [PWRAP_CRC_EN] = 0xE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) [PWRAP_TIMER_EN] = 0xE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) [PWRAP_WDT_UNIT] = 0xEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) [PWRAP_WDT_SRC_EN] = 0xF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) [PWRAP_WDT_SRC_EN_1] = 0xF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) [PWRAP_INT_GPS_AUXADC_CMD_ADDR] = 0x1DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) [PWRAP_INT_GPS_AUXADC_CMD] = 0x1E0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) [PWRAP_GPSINF_0_STA] = 0x1EC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) [PWRAP_GPSINF_1_STA] = 0x1F0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) [PWRAP_WACS2_CMD] = 0xC20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) [PWRAP_WACS2_RDATA] = 0xC24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) [PWRAP_WACS2_VLDCLR] = 0xC28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int mt8516_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) [PWRAP_MUX_SEL] = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) [PWRAP_WRAP_EN] = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) [PWRAP_DIO_EN] = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) [PWRAP_SIDLY] = 0xc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) [PWRAP_RDDMY] = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) [PWRAP_SI_CK_CON] = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) [PWRAP_CSHEXT_WRITE] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) [PWRAP_CSHEXT_READ] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) [PWRAP_CSLEXT_START] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) [PWRAP_CSLEXT_END] = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) [PWRAP_STAUPD_PRD] = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) [PWRAP_STAUPD_GRPEN] = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) [PWRAP_STAUPD_MAN_TRIG] = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) [PWRAP_STAUPD_STA] = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) [PWRAP_WRAP_STA] = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) [PWRAP_HARB_INIT] = 0x4c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) [PWRAP_HARB_HPRIO] = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) [PWRAP_HIPRIO_ARB_EN] = 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) [PWRAP_HARB_STA0] = 0x58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) [PWRAP_HARB_STA1] = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) [PWRAP_MAN_EN] = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) [PWRAP_MAN_CMD] = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) [PWRAP_MAN_RDATA] = 0x68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) [PWRAP_MAN_VLDCLR] = 0x6c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) [PWRAP_WACS0_EN] = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) [PWRAP_INIT_DONE0] = 0x74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) [PWRAP_WACS0_CMD] = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) [PWRAP_WACS0_RDATA] = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) [PWRAP_WACS0_VLDCLR] = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) [PWRAP_WACS1_EN] = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) [PWRAP_INIT_DONE1] = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) [PWRAP_WACS1_CMD] = 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) [PWRAP_WACS1_RDATA] = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) [PWRAP_WACS1_VLDCLR] = 0x94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) [PWRAP_WACS2_EN] = 0x98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) [PWRAP_INIT_DONE2] = 0x9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) [PWRAP_WACS2_CMD] = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) [PWRAP_WACS2_RDATA] = 0xa4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) [PWRAP_WACS2_VLDCLR] = 0xa8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) [PWRAP_INT_EN] = 0xac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) [PWRAP_INT_FLG_RAW] = 0xb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) [PWRAP_INT_FLG] = 0xb4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) [PWRAP_INT_CLR] = 0xb8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) [PWRAP_SIG_ADR] = 0xbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [PWRAP_SIG_MODE] = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [PWRAP_SIG_VALUE] = 0xc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [PWRAP_SIG_ERRVAL] = 0xc8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [PWRAP_CRC_EN] = 0xcc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) [PWRAP_TIMER_EN] = 0xd0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [PWRAP_TIMER_STA] = 0xd4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [PWRAP_WDT_UNIT] = 0xd8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [PWRAP_WDT_SRC_EN] = 0xdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [PWRAP_WDT_FLG] = 0xe0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [PWRAP_DEBUG_INT_SEL] = 0xe4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [PWRAP_DVFS_ADR0] = 0xe8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [PWRAP_DVFS_WDATA0] = 0xec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [PWRAP_DVFS_ADR1] = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [PWRAP_DVFS_WDATA1] = 0xf4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [PWRAP_DVFS_ADR2] = 0xf8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [PWRAP_DVFS_WDATA2] = 0xfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [PWRAP_DVFS_ADR3] = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [PWRAP_DVFS_WDATA3] = 0x104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [PWRAP_DVFS_ADR4] = 0x108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [PWRAP_DVFS_WDATA4] = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [PWRAP_DVFS_ADR5] = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [PWRAP_DVFS_WDATA5] = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [PWRAP_DVFS_ADR6] = 0x118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [PWRAP_DVFS_WDATA6] = 0x11c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [PWRAP_DVFS_ADR7] = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [PWRAP_DVFS_WDATA7] = 0x124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [PWRAP_SPMINF_STA] = 0x128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [PWRAP_CIPHER_KEY_SEL] = 0x12c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [PWRAP_CIPHER_IV_SEL] = 0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [PWRAP_CIPHER_EN] = 0x134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [PWRAP_CIPHER_RDY] = 0x138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [PWRAP_CIPHER_MODE] = 0x13c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [PWRAP_CIPHER_SWRST] = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [PWRAP_DCM_EN] = 0x144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [PWRAP_DCM_DBC_PRD] = 0x148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [PWRAP_SW_RST] = 0x168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [PWRAP_OP_TYPE] = 0x16c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [PWRAP_MSB_FIRST] = 0x170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) enum pmic_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PMIC_MT6323,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PMIC_MT6351,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PMIC_MT6357,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PMIC_MT6358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PMIC_MT6359,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PMIC_MT6380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PMIC_MT6397,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) enum pwrap_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PWRAP_MT2701,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PWRAP_MT6765,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PWRAP_MT6779,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PWRAP_MT6797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PWRAP_MT7622,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PWRAP_MT8135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PWRAP_MT8173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PWRAP_MT8183,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PWRAP_MT8516,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct pmic_wrapper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct pwrap_slv_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) const u32 *dew_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) enum pmic_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) const struct regmap_config *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Flags indicating the capability for the target slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) * pwrap operations are highly associated with the PMIC types,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * so the pointers added increases flexibility allowing determination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * which type is used by the detection through device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct pmic_wrapper {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) const struct pmic_wrapper_type *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) const struct pwrap_slv_type *slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct clk *clk_spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct clk *clk_wrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct reset_control *rstc_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) void __iomem *bridge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct pmic_wrapper_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) enum pwrap_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) u32 arb_en_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 int_en_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) u32 int1_en_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) u32 spi_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) u32 wdt_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* Flags indicating the capability for the target pwrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int (*init_reg_clock)(struct pmic_wrapper *wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int (*init_soc_specific)(struct pmic_wrapper *wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return readl(wrp->base + wrp->master->regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) writel(val, wrp->base + wrp->master->regs[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * Timeout issue sometimes caused by the last read command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * failed because pmic wrap could not got the FSM_VLDCLR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * in time after finishing WACS2_CMD. It made state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * still on FSM_VLDCLR and timeout next time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * Check the status of FSM and clear the vldclr to recovery the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (pwrap_is_fsm_vldclr(wrp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) (val & PWRAP_STATE_SYNC_IDLE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) bool (*fp)(struct pmic_wrapper *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) timeout = jiffies + usecs_to_jiffies(10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return fp(wrp) ? 0 : -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (fp(wrp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) pwrap_leave_fsm_vldclr(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) int ret, msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) *rdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) for (msb = 0; msb < 2; msb++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) pwrap_leave_fsm_vldclr(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PWRAP_WACS2_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PWRAP_WACS2_RDATA)) << (16 * msb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return wrp->slave->pwrap_read(wrp, adr, rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) pwrap_leave_fsm_vldclr(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PWRAP_WACS2_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int ret, msb, rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) for (msb = 0; msb < 2; msb++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) pwrap_leave_fsm_vldclr(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ((wdata >> (msb * 16)) & 0xffff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PWRAP_WACS2_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * The pwrap_read operation is the requirement of hardware used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * for the synchronization between two successive 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * pwrap_writel operations composing one 32-bit bus writing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * Otherwise, we'll find the result fails on the lower 16-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * pwrap writing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (!msb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) pwrap_read(wrp, adr, &rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return wrp->slave->pwrap_write(wrp, adr, wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return pwrap_read(context, adr, rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return pwrap_write(context, adr, wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) pwrap_writel(wrp, 1, PWRAP_MAN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) pwrap_writel(wrp, 0, PWRAP_DIO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PWRAP_MAN_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) PWRAP_MAN_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PWRAP_MAN_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PWRAP_MAN_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) pwrap_writel(wrp, 0, PWRAP_MAN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * pwrap_init_sidly - configure serial input delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * delay. Do a read test with all possible values and chose the best delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int pwrap_init_sidly(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) u32 rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) u32 pass = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) signed char dly[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pwrap_writel(wrp, i, PWRAP_SIDLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) &rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (rdata == PWRAP_DEW_READ_TEST_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) pass |= 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (dly[pass] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) u32 rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* Enable dual IO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* Check IDLE & INIT_DONE in advance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = pwrap_wait_for_state(wrp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) pwrap_is_fsm_idle_and_sync_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) pwrap_writel(wrp, 1, PWRAP_DIO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* Read Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) pwrap_read(wrp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (rdata != PWRAP_DEW_READ_TEST_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(wrp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) "Read failed on DIO mode: 0x%04x!=0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PWRAP_DEW_READ_TEST_VAL, rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) * pwrap_init_chip_select_ext is used to configure CS extension time for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) * phase during data transactions on the pwrap bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) u8 hext_read, u8 lext_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) u8 lext_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * After finishing a write and read transaction, extends CS high time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * to be at least xT of BUS CLK as hext_write and hext_read specifies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * Extends CS low time after CSL and before CSH command to be at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * least xT of BUS CLK as lext_start and lext_end specifies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) switch (wrp->master->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) case PWRAP_MT8173:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) case PWRAP_MT8135:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) switch (wrp->slave->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) case PMIC_MT6397:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) case PMIC_MT6323:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) u32 rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) &rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return rdata == 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static int pwrap_init_cipher(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) u32 rdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) switch (wrp->master->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) case PWRAP_MT8135:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) case PWRAP_MT2701:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) case PWRAP_MT6765:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) case PWRAP_MT6779:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) case PWRAP_MT6797:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) case PWRAP_MT8173:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) case PWRAP_MT8516:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) case PWRAP_MT7622:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) case PWRAP_MT8183:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /* Config cipher mode @PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) switch (wrp->slave->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) case PMIC_MT6397:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) case PMIC_MT6323:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) case PMIC_MT6351:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) case PMIC_MT6357:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* wait for cipher data ready@AP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* wait for cipher data ready@PMIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) dev_err(wrp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) "timeout waiting for cipher data ready@PMIC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* wait for cipher mode idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* Write Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) PWRAP_DEW_WRITE_TEST_VAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) &rdata) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static int pwrap_init_security(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* Enable encryption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret = pwrap_init_cipher(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* Signature checking - using CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (pwrap_write(wrp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) PWRAP_SIG_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) pwrap_writel(wrp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* enable pwrap events and pwrap bridge in AP side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* enable PMIC event out and sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) 0x1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) 0xffff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dev_err(wrp->dev, "enable dewrap fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /* PMIC_DEWRAP enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) 0x1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) 0xffff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) dev_err(wrp->dev, "enable dewrap fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /* GPS_INTF initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) switch (wrp->slave->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) case PMIC_MT6323:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* enable 2wire SPI master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) pwrap_writel(wrp, 1, PWRAP_CRC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static int pwrap_init(struct pmic_wrapper *wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (wrp->rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) reset_control_reset(wrp->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (wrp->rstc_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) reset_control_reset(wrp->rstc_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (wrp->master->type == PWRAP_MT8173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* Enable DCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) pwrap_writel(wrp, 3, PWRAP_DCM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* Reset SPI slave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ret = pwrap_reset_spislave(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ret = wrp->master->init_reg_clock(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* Setup serial input delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ret = pwrap_init_sidly(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* Enable dual I/O mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ret = pwrap_init_dual_io(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) /* Enable security on bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ret = pwrap_init_security(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (wrp->master->type == PWRAP_MT8135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) if (wrp->master->init_soc_specific) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) ret = wrp->master->init_soc_specific(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /* Setup the init done registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) u32 rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct pmic_wrapper *wrp = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static const struct regmap_config pwrap_regmap_config16 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .reg_read = pwrap_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .reg_write = pwrap_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .max_register = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static const struct regmap_config pwrap_regmap_config32 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .reg_read = pwrap_regmap_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .reg_write = pwrap_regmap_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .max_register = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static const struct pwrap_slv_type pmic_mt6323 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .dew_regs = mt6323_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .type = PMIC_MT6323,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .regmap = &pwrap_regmap_config16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) PWRAP_SLV_CAP_SECURITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .pwrap_read = pwrap_read16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .pwrap_write = pwrap_write16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) static const struct pwrap_slv_type pmic_mt6351 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .dew_regs = mt6351_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .type = PMIC_MT6351,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .regmap = &pwrap_regmap_config16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .caps = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .pwrap_read = pwrap_read16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .pwrap_write = pwrap_write16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static const struct pwrap_slv_type pmic_mt6357 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .dew_regs = mt6357_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .type = PMIC_MT6357,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .regmap = &pwrap_regmap_config16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .caps = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .pwrap_read = pwrap_read16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .pwrap_write = pwrap_write16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static const struct pwrap_slv_type pmic_mt6358 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .dew_regs = mt6358_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .type = PMIC_MT6358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .regmap = &pwrap_regmap_config16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .pwrap_read = pwrap_read16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .pwrap_write = pwrap_write16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) static const struct pwrap_slv_type pmic_mt6359 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .dew_regs = mt6359_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .type = PMIC_MT6359,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .regmap = &pwrap_regmap_config16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .caps = PWRAP_SLV_CAP_DUALIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .pwrap_read = pwrap_read16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .pwrap_write = pwrap_write16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static const struct pwrap_slv_type pmic_mt6380 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .dew_regs = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .type = PMIC_MT6380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .regmap = &pwrap_regmap_config32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .caps = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .pwrap_read = pwrap_read32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .pwrap_write = pwrap_write32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static const struct pwrap_slv_type pmic_mt6397 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .dew_regs = mt6397_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .type = PMIC_MT6397,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .regmap = &pwrap_regmap_config16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) PWRAP_SLV_CAP_SECURITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .pwrap_read = pwrap_read16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .pwrap_write = pwrap_write16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static const struct of_device_id of_slave_match_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .compatible = "mediatek,mt6323",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .data = &pmic_mt6323,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .compatible = "mediatek,mt6351",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .data = &pmic_mt6351,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .compatible = "mediatek,mt6357",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .data = &pmic_mt6357,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .compatible = "mediatek,mt6358",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .data = &pmic_mt6358,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .compatible = "mediatek,mt6359",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .data = &pmic_mt6359,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* The MT6380 PMIC only implements a regulator, so we bind it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) * directly instead of using a MFD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .compatible = "mediatek,mt6380-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .data = &pmic_mt6380,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .compatible = "mediatek,mt6397",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .data = &pmic_mt6397,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static const struct pmic_wrapper_type pwrap_mt2701 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .regs = mt2701_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .type = PWRAP_MT2701,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .arb_en_all = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .int_en_all = ~(u32)(BIT(31) | BIT(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .int1_en_all = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .init_reg_clock = pwrap_mt2701_init_reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .init_soc_specific = pwrap_mt2701_init_soc_specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static const struct pmic_wrapper_type pwrap_mt6765 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .regs = mt6765_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .type = PWRAP_MT6765,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .arb_en_all = 0x3fd35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .int_en_all = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .init_reg_clock = pwrap_common_init_reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .init_soc_specific = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static const struct pmic_wrapper_type pwrap_mt6779 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .regs = mt6779_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .type = PWRAP_MT6779,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .arb_en_all = 0xfbb7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .int_en_all = 0xfffffffe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .int1_en_all = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .caps = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .init_reg_clock = pwrap_common_init_reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .init_soc_specific = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static const struct pmic_wrapper_type pwrap_mt6797 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .regs = mt6797_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .type = PWRAP_MT6797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .arb_en_all = 0x01fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .int_en_all = 0xffffffc6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .int1_en_all = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .init_reg_clock = pwrap_common_init_reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .init_soc_specific = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static const struct pmic_wrapper_type pwrap_mt7622 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .regs = mt7622_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .type = PWRAP_MT7622,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .arb_en_all = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .int_en_all = ~(u32)BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .int1_en_all = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .init_reg_clock = pwrap_common_init_reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .init_soc_specific = pwrap_mt7622_init_soc_specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static const struct pmic_wrapper_type pwrap_mt8135 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .regs = mt8135_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .type = PWRAP_MT8135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .arb_en_all = 0x1ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .int_en_all = ~(u32)(BIT(31) | BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .int1_en_all = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .init_reg_clock = pwrap_common_init_reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .init_soc_specific = pwrap_mt8135_init_soc_specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static const struct pmic_wrapper_type pwrap_mt8173 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .regs = mt8173_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .type = PWRAP_MT8173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) .arb_en_all = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .int_en_all = ~(u32)(BIT(31) | BIT(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .int1_en_all = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .init_reg_clock = pwrap_common_init_reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) .init_soc_specific = pwrap_mt8173_init_soc_specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static const struct pmic_wrapper_type pwrap_mt8183 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .regs = mt8183_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .type = PWRAP_MT8183,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .arb_en_all = 0x3fa75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .int_en_all = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .int1_en_all = 0xeef7ffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .init_reg_clock = pwrap_common_init_reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .init_soc_specific = pwrap_mt8183_init_soc_specific,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static struct pmic_wrapper_type pwrap_mt8516 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .regs = mt8516_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .type = PWRAP_MT8516,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .arb_en_all = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .int_en_all = ~(u32)(BIT(31) | BIT(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .caps = PWRAP_CAP_DCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .init_reg_clock = pwrap_mt2701_init_reg_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .init_soc_specific = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static const struct of_device_id of_pwrap_match_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) .compatible = "mediatek,mt2701-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .data = &pwrap_mt2701,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .compatible = "mediatek,mt6765-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .data = &pwrap_mt6765,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .compatible = "mediatek,mt6779-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .data = &pwrap_mt6779,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .compatible = "mediatek,mt6797-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .data = &pwrap_mt6797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .compatible = "mediatek,mt7622-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .data = &pwrap_mt7622,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .compatible = "mediatek,mt8135-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .data = &pwrap_mt8135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .compatible = "mediatek,mt8173-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .data = &pwrap_mt8173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .compatible = "mediatek,mt8183-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .data = &pwrap_mt8183,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .compatible = "mediatek,mt8516-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .data = &pwrap_mt8516,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static int pwrap_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) struct pmic_wrapper *wrp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) const struct of_device_id *of_slave_id = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (np->child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) of_slave_id = of_match_node(of_slave_match_tbl, np->child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (!of_slave_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (!wrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) platform_set_drvdata(pdev, wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) wrp->master = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) wrp->slave = of_slave_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) wrp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) wrp->base = devm_ioremap_resource(wrp->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (IS_ERR(wrp->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return PTR_ERR(wrp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if (IS_ERR(wrp->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) ret = PTR_ERR(wrp->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) "pwrap-bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if (IS_ERR(wrp->bridge_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) return PTR_ERR(wrp->bridge_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) "pwrap-bridge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (IS_ERR(wrp->rstc_bridge)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ret = PTR_ERR(wrp->rstc_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) dev_dbg(wrp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) "cannot get pwrap-bridge reset: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (IS_ERR(wrp->clk_spi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) dev_dbg(wrp->dev, "failed to get clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) PTR_ERR(wrp->clk_spi));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) return PTR_ERR(wrp->clk_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) if (IS_ERR(wrp->clk_wrap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) dev_dbg(wrp->dev, "failed to get clock: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) PTR_ERR(wrp->clk_wrap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) return PTR_ERR(wrp->clk_wrap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ret = clk_prepare_enable(wrp->clk_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ret = clk_prepare_enable(wrp->clk_wrap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) goto err_out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) /* Enable internal dynamic clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) pwrap_writel(wrp, 1, PWRAP_DCM_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) * The PMIC could already be initialized by the bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) * Skip initialization here in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ret = pwrap_init(wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) dev_dbg(wrp->dev, "init failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) goto err_out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) dev_dbg(wrp->dev, "initialization isn't finished\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) goto err_out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /* Initialize watchdog, may not be done by the bootloader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) * Since STAUPD was not used on mt8173 platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) * so STAUPD of WDT_SRC which should be turned off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) * We add INT1 interrupt to handle starvation and request exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) * If we support it, we should enable it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) "mt-pmic-pwrap", wrp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) goto err_out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (IS_ERR(wrp->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) ret = PTR_ERR(wrp->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) goto err_out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) ret = of_platform_populate(np, NULL, NULL, wrp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) goto err_out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) err_out2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) clk_disable_unprepare(wrp->clk_wrap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) err_out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) clk_disable_unprepare(wrp->clk_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) static struct platform_driver pwrap_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .name = "mt-pmic-pwrap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .of_match_table = of_match_ptr(of_pwrap_match_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .probe = pwrap_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) module_platform_driver(pwrap_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) MODULE_AUTHOR("Flora Fu, MediaTek");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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