Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: James Liao <jamesjj.liao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/soc/mediatek/mtk-mmsys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DISP_REG_CONFIG_OUT_SEL			0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DISP_REG_CONFIG_DSI_SEL			0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define DISP_REG_CONFIG_DPI_SEL			0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define OVL0_MOUT_EN_COLOR0			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define OD_MOUT_EN_RDMA0			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define OD1_MOUT_EN_RDMA1			BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define UFOE_MOUT_EN_DSI0			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define COLOR0_SEL_IN_OVL0			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define OVL1_MOUT_EN_COLOR1			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define GAMMA_MOUT_EN_RDMA1			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RDMA0_SOUT_DPI0				0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RDMA0_SOUT_DPI1				0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RDMA0_SOUT_DSI1				0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RDMA0_SOUT_DSI2				0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RDMA0_SOUT_DSI3				0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RDMA1_SOUT_DPI0				0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RDMA1_SOUT_DPI1				0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RDMA1_SOUT_DSI1				0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define RDMA1_SOUT_DSI2				0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RDMA1_SOUT_DSI3				0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RDMA2_SOUT_DPI0				0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RDMA2_SOUT_DPI1				0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RDMA2_SOUT_DSI1				0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RDMA2_SOUT_DSI2				0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RDMA2_SOUT_DSI3				0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define DPI0_SEL_IN_RDMA1			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define DPI0_SEL_IN_RDMA2			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DPI1_SEL_IN_RDMA1			(0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define DPI1_SEL_IN_RDMA2			(0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define DSI0_SEL_IN_RDMA1			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define DSI0_SEL_IN_RDMA2			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define DSI1_SEL_IN_RDMA1			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define DSI1_SEL_IN_RDMA2			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define DSI2_SEL_IN_RDMA1			(0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define DSI2_SEL_IN_RDMA2			(0x4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define DSI3_SEL_IN_RDMA1			(0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define DSI3_SEL_IN_RDMA2			(0x4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define COLOR1_SEL_IN_OVL1			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define OVL_MOUT_EN_RDMA			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define BLS_TO_DPI_RDMA1_TO_DSI			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define DSI_SEL_IN_BLS				0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DPI_SEL_IN_BLS				0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DSI_SEL_IN_RDMA				0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) struct mtk_mmsys_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	const char *clk_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.clk_driver = "clk-mt2701-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.clk_driver = "clk-mt2712-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.clk_driver = "clk-mt6779-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.clk_driver = "clk-mt6797-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.clk_driver = "clk-mt8173-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.clk_driver = "clk-mt8183-mm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 					  enum mtk_ddp_comp_id next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 					  unsigned int *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		value = OVL0_MOUT_EN_COLOR0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		value = OVL_MOUT_EN_RDMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		value = OD_MOUT_EN_RDMA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		value = UFOE_MOUT_EN_DSI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		value = OVL1_MOUT_EN_COLOR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		value = GAMMA_MOUT_EN_RDMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		value = OD1_MOUT_EN_RDMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		value = RDMA0_SOUT_DPI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		value = RDMA0_SOUT_DPI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		value = RDMA0_SOUT_DSI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		value = RDMA0_SOUT_DSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		value = RDMA0_SOUT_DSI3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		value = RDMA1_SOUT_DSI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		value = RDMA1_SOUT_DSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		value = RDMA1_SOUT_DSI3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		value = RDMA1_SOUT_DPI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		value = RDMA1_SOUT_DPI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		value = RDMA2_SOUT_DPI0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		value = RDMA2_SOUT_DPI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		value = RDMA2_SOUT_DSI1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		value = RDMA2_SOUT_DSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		value = RDMA2_SOUT_DSI3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 					 enum mtk_ddp_comp_id next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 					 unsigned int *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		value = COLOR0_SEL_IN_OVL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		value = DPI0_SEL_IN_RDMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		value = DPI1_SEL_IN_RDMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		value = DSI0_SEL_IN_RDMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		value = DSI1_SEL_IN_RDMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		value = DSI2_SEL_IN_RDMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		value = DSI3_SEL_IN_RDMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		value = DPI0_SEL_IN_RDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		value = DPI1_SEL_IN_RDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		value = DSI0_SEL_IN_RDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		value = DSI1_SEL_IN_RDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		value = DSI2_SEL_IN_RDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		value = DSI3_SEL_IN_RDMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		value = COLOR1_SEL_IN_OVL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		*addr = DISP_REG_CONFIG_DSI_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		value = DSI_SEL_IN_BLS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 				   enum mtk_ddp_comp_id cur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 				   enum mtk_ddp_comp_id next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			       config_regs + DISP_REG_CONFIG_OUT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			       config_regs + DISP_REG_CONFIG_OUT_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		writel_relaxed(DSI_SEL_IN_RDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			       config_regs + DISP_REG_CONFIG_DSI_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		writel_relaxed(DPI_SEL_IN_BLS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			       config_regs + DISP_REG_CONFIG_DPI_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void mtk_mmsys_ddp_connect(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			   enum mtk_ddp_comp_id cur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			   enum mtk_ddp_comp_id next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	void __iomem *config_regs = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	unsigned int addr, value, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		reg = readl_relaxed(config_regs + addr) | value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		writel_relaxed(reg, config_regs + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		reg = readl_relaxed(config_regs + addr) | value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		writel_relaxed(reg, config_regs + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) void mtk_mmsys_ddp_disconnect(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			      enum mtk_ddp_comp_id cur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			      enum mtk_ddp_comp_id next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	void __iomem *config_regs = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	unsigned int addr, value, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		reg = readl_relaxed(config_regs + addr) & ~value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		writel_relaxed(reg, config_regs + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		reg = readl_relaxed(config_regs + addr) & ~value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		writel_relaxed(reg, config_regs + addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int mtk_mmsys_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	const struct mtk_mmsys_driver_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct platform_device *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct platform_device *drm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	void __iomem *config_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	config_regs = devm_ioremap_resource(dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (IS_ERR(config_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		ret = PTR_ERR(config_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	platform_set_drvdata(pdev, config_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	clks = platform_device_register_data(&pdev->dev, data->clk_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 					     PLATFORM_DEVID_AUTO, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (IS_ERR(clks))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return PTR_ERR(clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					    PLATFORM_DEVID_AUTO, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (IS_ERR(drm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		platform_device_unregister(clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return PTR_ERR(drm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct of_device_id of_match_mtk_mmsys[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		.compatible = "mediatek,mt2701-mmsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		.data = &mt2701_mmsys_driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.compatible = "mediatek,mt2712-mmsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.data = &mt2712_mmsys_driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.compatible = "mediatek,mt6779-mmsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.data = &mt6779_mmsys_driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		.compatible = "mediatek,mt6797-mmsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		.data = &mt6797_mmsys_driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.compatible = "mediatek,mt8173-mmsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		.data = &mt8173_mmsys_driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		.compatible = "mediatek,mt8183-mmsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		.data = &mt8183_mmsys_driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static struct platform_driver mtk_mmsys_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		.name = "mtk-mmsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		.of_match_table = of_match_mtk_mmsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.probe = mtk_mmsys_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) builtin_platform_driver(mtk_mmsys_drv);