^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 Christoph Hellwig.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2019 Western Digital Corporation or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define K210_SYSCTL_CLK0_FREQ 26000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Registers base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define K210_SYSCTL_SYSCTL_BASE_ADDR 0x50440000ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define K210_SYSCTL_PLL0 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define K210_SYSCTL_PLL1 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* clkr: 4bits, clkf1: 6bits, clkod: 4bits, bwadj: 4bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PLL_RESET (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PLL_PWR (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PLL_INTFB (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLL_BYPASS (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLL_TEST (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_OUT_EN (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLL_TEST_EN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define K210_SYSCTL_PLL_LOCK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PLL0_LOCK1 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PLL0_LOCK2 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PLL0_SLIP_CLEAR (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PLL0_TEST_CLK_OUT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLL1_LOCK1 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLL1_LOCK2 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PLL1_SLIP_CLEAR (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PLL1_TEST_CLK_OUT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PLL2_LOCK1 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLL2_LOCK2 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLL2_SLIP_CLEAR (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLL2_TEST_CLK_OUT (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define K210_SYSCTL_CLKSEL0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLKSEL_ACLK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define K210_SYSCTL_CLKEN_CENT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLKEN_CPU (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLKEN_SRAM0 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLKEN_SRAM1 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLKEN_APB0 (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLKEN_APB1 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLKEN_APB2 (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define K210_SYSCTL_CLKEN_PERI 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLKEN_ROM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLKEN_DMA (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLKEN_AI (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLKEN_DVP (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLKEN_FFT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLKEN_GPIO (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLKEN_SPI0 (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLKEN_SPI1 (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLKEN_SPI2 (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLKEN_SPI3 (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLKEN_I2S0 (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLKEN_I2S1 (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLKEN_I2S2 (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLKEN_I2C0 (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLKEN_I2C1 (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLKEN_I2C2 (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLKEN_UART1 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLKEN_UART2 (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLKEN_UART3 (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLKEN_AES (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLKEN_FPIO (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLKEN_TIMER0 (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLKEN_TIMER1 (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLKEN_TIMER2 (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLKEN_WDT0 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLKEN_WDT1 (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLKEN_SHA (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLKEN_OTP (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLKEN_RTC (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct k210_sysctl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void k210_set_bits(u32 val, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writel(readl(reg) | val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void k210_clear_bits(u32 val, void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(readl(reg) & ~val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void k210_pll1_enable(void __iomem *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) val = readl(regs + K210_SYSCTL_PLL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val &= ~GENMASK(19, 0); /* clkr1 = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) val |= FIELD_PREP(GENMASK(9, 4), 0x3B); /* clkf1 = 59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) val |= FIELD_PREP(GENMASK(13, 10), 0x3); /* clkod1 = 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) val |= FIELD_PREP(GENMASK(19, 14), 0x3B); /* bwadj1 = 59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) writel(val, regs + K210_SYSCTL_PLL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) k210_clear_bits(PLL_BYPASS, regs + K210_SYSCTL_PLL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) k210_set_bits(PLL_PWR, regs + K210_SYSCTL_PLL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Reset the pll. The magic NOPs come from the Kendryte reference SDK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) k210_clear_bits(PLL_RESET, regs + K210_SYSCTL_PLL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) k210_set_bits(PLL_RESET, regs + K210_SYSCTL_PLL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) nop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) nop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) k210_clear_bits(PLL_RESET, regs + K210_SYSCTL_PLL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) val = readl(regs + K210_SYSCTL_PLL_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (val & PLL1_LOCK2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writel(val | PLL1_SLIP_CLEAR, regs + K210_SYSCTL_PLL_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static unsigned long k210_sysctl_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct k210_sysctl *s = container_of(hw, struct k210_sysctl, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 clksel0, pll0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u64 pll0_freq, clkr0, clkf0, clkod0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * If the clock selector is not set, use the base frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Otherwise, use PLL0 frequency with a frequency divisor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) clksel0 = readl(s->regs + K210_SYSCTL_CLKSEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!(clksel0 & CLKSEL_ACLK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return K210_SYSCTL_CLK0_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Get PLL0 frequency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * freq = base frequency * clkf0 / (clkr0 * clkod0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pll0 = readl(s->regs + K210_SYSCTL_PLL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clkr0 = 1 + FIELD_GET(GENMASK(3, 0), pll0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clkf0 = 1 + FIELD_GET(GENMASK(9, 4), pll0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clkod0 = 1 + FIELD_GET(GENMASK(13, 10), pll0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pll0_freq = clkf0 * K210_SYSCTL_CLK0_FREQ / (clkr0 * clkod0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Get the frequency divisor from the clock selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return pll0_freq / (2ULL << FIELD_GET(0x00000006, clksel0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct clk_ops k210_sysctl_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .recalc_rate = k210_sysctl_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct clk_init_data k210_clk_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .name = "k210-sysctl-pll1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .ops = &k210_sysctl_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int k210_sysctl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct k210_sysctl *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pr_info("Kendryte K210 SoC sysctl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) s->regs = devm_ioremap_resource(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) platform_get_resource(pdev, IORESOURCE_MEM, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (IS_ERR(s->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return PTR_ERR(s->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) s->hw.init = &k210_clk_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) error = devm_clk_hw_register(&pdev->dev, &s->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(&pdev->dev, "failed to register clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) error = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &s->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(&pdev->dev, "adding clk provider failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct of_device_id k210_sysctl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .compatible = "kendryte,k210-sysctl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct platform_driver k210_sysctl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "k210-sysctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .of_match_table = k210_sysctl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .probe = k210_sysctl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int __init k210_sysctl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return platform_driver_register(&k210_sysctl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) core_initcall(k210_sysctl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * This needs to be called very early during initialization, given that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * PLL1 needs to be enabled to be able to use all SRAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void __init k210_soc_early_init(const void *fdt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) regs = ioremap(K210_SYSCTL_SYSCTL_BASE_ADDR, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) panic("K210 sysctl ioremap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Enable PLL1 to make the KPU SRAM useable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) k210_pll1_enable(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) k210_set_bits(PLL_OUT_EN, regs + K210_SYSCTL_PLL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) k210_set_bits(CLKEN_CPU | CLKEN_SRAM0 | CLKEN_SRAM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) regs + K210_SYSCTL_CLKEN_CENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) k210_set_bits(CLKEN_ROM | CLKEN_TIMER0 | CLKEN_RTC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) regs + K210_SYSCTL_CLKEN_PERI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) k210_set_bits(CLKSEL_ACLK, regs + K210_SYSCTL_CLKSEL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SOC_EARLY_INIT_DECLARE(generic_k210, "kendryte,k210", k210_soc_early_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #ifdef CONFIG_SOC_KENDRYTE_K210_DTB_BUILTIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * Generic entry for the default k210.dtb embedded DTB for boards with:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * - Vendor ID: 0x4B5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * - Arch ID: 0xE59889E6A5A04149 (= "Canaan AI" in UTF-8 encoded Chinese)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * - Impl ID: 0x4D41495832303030 (= "MAIX2000")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * These values are reported by the SiPEED MAXDUINO, SiPEED MAIX GO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * SiPEED Dan dock boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) SOC_BUILTIN_DTB_DECLARE(k210, 0x4B5, 0xE59889E6A5A04149, 0x4D41495832303030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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