^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2011-2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GPC_CNTR 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GPC_PGC_CTRL_OFFS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GPC_PGC_PUPSCR_OFFS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GPC_PGC_PDNSCR_OFFS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GPC_PGC_SW2ISO_SHIFT 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GPC_PGC_SW_SHIFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GPC_PGC_PCI_PDN 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GPC_PGC_PCI_SR 0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPC_PGC_GPU_PDN 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPC_PGC_GPU_PUPSCR 0x264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GPC_PGC_GPU_PDNSCR 0x268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GPC_PGC_GPU_SR 0x26c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GPC_PGC_DISP_PDN 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GPC_PGC_DISP_SR 0x24c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPU_VPU_PUP_REQ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPU_VPU_PDN_REQ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPC_CLK_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PGC_DOMAIN_FLAG_NO_PD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct imx_pm_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct generic_pm_domain base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct regulator *supply;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk *clk[GPC_CLK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int reg_offs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) signed char cntr_pdn_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int ipg_rate_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline struct imx_pm_domain *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) to_imx_pm_domain(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return container_of(genpd, struct imx_pm_domain, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int iso, iso2sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Read ISO and ISO2SW power down delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PDNSCR_OFFS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) iso = val & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) iso2sw = (val >> 8) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Gate off domain when powered down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Request GPC to power down domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val = BIT(pd->cntr_pdn_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Wait ISO + ISO2SW IPG clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (pd->supply)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) regulator_disable(pd->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 val, req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (pd->supply) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = regulator_enable(pd->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) pr_err("%s: failed to enable regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Enable reset clocks for all devices in the domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) for (i = 0; i < pd->num_clks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk_prepare_enable(pd->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Gate off domain when powered down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x1, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Request GPC to power up domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) req = BIT(pd->cntr_pdn_bit + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) regmap_update_bits(pd->regmap, GPC_CNTR, req, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Wait for the PGC to handle the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = regmap_read_poll_timeout(pd->regmap, GPC_CNTR, val, !(val & req),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 1, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pr_err("powerup request on domain %s timed out\n", genpd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Wait for reset to propagate through peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) usleep_range(5, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Disable reset clocks for all devices in the domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) for (i = 0; i < pd->num_clks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk_disable_unprepare(pd->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int imx_pgc_get_clocks(struct device *dev, struct imx_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 0; ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct clk *clk = of_clk_get(dev->of_node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (i >= GPC_CLK_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) domain->clk[i] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) domain->num_clks = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clk_put(domain->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void imx_pgc_put_clocks(struct imx_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (i = domain->num_clks - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clk_put(domain->clk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int imx_pgc_parse_dt(struct device *dev, struct imx_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* try to get the domain supply regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) domain->supply = devm_regulator_get_optional(dev, "power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (IS_ERR(domain->supply)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (PTR_ERR(domain->supply) == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) domain->supply = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return PTR_ERR(domain->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* try to get all clocks needed for reset propagation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return imx_pgc_get_clocks(dev, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int imx_pgc_power_domain_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct imx_pm_domain *domain = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* if this PD is associated with a DT node try to parse it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = imx_pgc_parse_dt(dev, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* initially power on the domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (domain->base.power_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) domain->base.power_on(&domain->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pm_genpd_init(&domain->base, NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = of_genpd_add_provider_simple(dev->of_node, &domain->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto genpd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE_CONSUMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) genpd_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pm_genpd_remove(&domain->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) imx_pgc_put_clocks(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int imx_pgc_power_domain_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct imx_pm_domain *domain = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) of_genpd_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pm_genpd_remove(&domain->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) imx_pgc_put_clocks(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct platform_device_id imx_pgc_power_domain_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { "imx-pgc-power-domain"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct platform_driver imx_pgc_power_domain_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "imx-pgc-pd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .probe = imx_pgc_power_domain_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .remove = imx_pgc_power_domain_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .id_table = imx_pgc_power_domain_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) builtin_platform_driver(imx_pgc_power_domain_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GPC_PGC_DOMAIN_ARM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GPC_PGC_DOMAIN_PU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GPC_PGC_DOMAIN_DISPLAY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define GPC_PGC_DOMAIN_PCI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct genpd_power_state imx6_pm_domain_pu_state = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .power_off_latency_ns = 25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .power_on_latency_ns = 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct imx_pm_domain imx_gpc_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) [GPC_PGC_DOMAIN_ARM] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "ARM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .flags = GENPD_FLAG_ALWAYS_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [GPC_PGC_DOMAIN_PU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .name = "PU",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .power_off = imx6_pm_domain_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .power_on = imx6_pm_domain_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .states = &imx6_pm_domain_pu_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .state_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .reg_offs = 0x260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .cntr_pdn_bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [GPC_PGC_DOMAIN_DISPLAY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "DISPLAY",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .power_off = imx6_pm_domain_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .power_on = imx6_pm_domain_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .reg_offs = 0x240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .cntr_pdn_bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) [GPC_PGC_DOMAIN_PCI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = "PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .power_off = imx6_pm_domain_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .power_on = imx6_pm_domain_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .reg_offs = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .cntr_pdn_bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct imx_gpc_dt_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int num_domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) bool err009619_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) bool err006287_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct imx_gpc_dt_data imx6q_dt_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .num_domains = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .err009619_present = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .err006287_present = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct imx_gpc_dt_data imx6qp_dt_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .num_domains = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .err009619_present = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .err006287_present = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct imx_gpc_dt_data imx6sl_dt_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .num_domains = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .err009619_present = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .err006287_present = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct imx_gpc_dt_data imx6sx_dt_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .num_domains = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .err009619_present = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .err006287_present = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct of_device_id imx_gpc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { .compatible = "fsl,imx6sx-gpc", .data = &imx6sx_dt_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const struct regmap_range yes_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) regmap_reg_range(GPC_CNTR, GPC_CNTR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) regmap_reg_range(GPC_PGC_PCI_PDN, GPC_PGC_PCI_SR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) regmap_reg_range(GPC_PGC_GPU_PDN, GPC_PGC_GPU_SR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) regmap_reg_range(GPC_PGC_DISP_PDN, GPC_PGC_DISP_SR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct regmap_access_table access_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .yes_ranges = yes_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .n_yes_ranges = ARRAY_SIZE(yes_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct regmap_config imx_gpc_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .rd_table = &access_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .wr_table = &access_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .max_register = 0x2ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) &imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) &imx_gpc_domains[GPC_PGC_DOMAIN_PU].base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static struct genpd_onecell_data imx_gpc_onecell_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .domains = imx_gpc_onecell_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .num_domains = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int num_domains)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct imx_pm_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < num_domains; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) domain = &imx_gpc_domains[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) domain->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) domain->ipg_rate_mhz = 66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (i == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) domain->supply = devm_regulator_get(dev, "pu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (IS_ERR(domain->supply))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return PTR_ERR(domain->supply);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = imx_pgc_get_clocks(dev, domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) goto clk_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) domain->base.power_on(&domain->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) for (i = 0; i < num_domains; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pm_genpd_init(&imx_gpc_domains[i].base, NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = of_genpd_add_provider_onecell(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) &imx_gpc_onecell_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto genpd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) genpd_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) for (i = 0; i < num_domains; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pm_genpd_remove(&imx_gpc_domains[i].base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) clk_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int imx_gpc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) of_match_device(imx_gpc_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) const struct imx_gpc_dt_data *of_id_data = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct device_node *pgc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* bail out if DT too old and doesn't provide the necessary info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) !pgc_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &imx_gpc_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_err(&pdev->dev, "failed to init regmap: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Disable PU power down by runtime PM if ERR009619 is present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * The PRE clock will be paused for several cycles when turning on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * PU domain LDO from power down state. If PRE is in use at that time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * the IPU/PRG cannot get the correct display data from the PRE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * This is not a concern when the whole system enters suspend state, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * it's safe to power down PU in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (of_id_data->err009619_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) imx_gpc_domains[GPC_PGC_DOMAIN_PU].base.flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) GENPD_FLAG_RPM_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Keep DISP always on if ERR006287 is present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (of_id_data->err006287_present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) imx_gpc_domains[GPC_PGC_DOMAIN_DISPLAY].base.flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) GENPD_FLAG_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!pgc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) of_id_data->num_domains);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct imx_pm_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct platform_device *pd_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct clk *ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int ipg_rate_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int domain_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ipg_clk = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (IS_ERR(ipg_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return PTR_ERR(ipg_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ipg_rate_mhz = clk_get_rate(ipg_clk) / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) for_each_child_of_node(pgc_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = of_property_read_u32(np, "reg", &domain_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (domain_index >= of_id_data->num_domains)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pd_pdev = platform_device_alloc("imx-pgc-power-domain",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) domain_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!pd_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = platform_device_add_data(pd_pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &imx_gpc_domains[domain_index],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) sizeof(imx_gpc_domains[domain_index]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) platform_device_put(pd_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) domain = pd_pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) domain->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) domain->ipg_rate_mhz = ipg_rate_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pd_pdev->dev.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pd_pdev->dev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ret = platform_device_add(pd_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) platform_device_put(pd_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int imx_gpc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct device_node *pgc_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* bail out if DT too old and doesn't provide the necessary info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) !pgc_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * If the old DT binding is used the toplevel driver needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * de-register the power domains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!pgc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) of_genpd_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct platform_driver imx_gpc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .name = "imx-gpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .of_match_table = imx_gpc_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .probe = imx_gpc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .remove = imx_gpc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) builtin_platform_driver(imx_gpc_driver)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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