Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * QE USB routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2006 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *               Shlomi Gridish <gridish@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *               Jerry Huang <Chang-Ming.Huang@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (c) MontaVista Software, Inc. 2008.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *               Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <soc/fsl/qe/immap_qe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <soc/fsl/qe/qe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int qe_usb_clock_set(enum qe_clock clk, int rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct qe_mux __iomem *mux = &qe_immr->qmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	switch (clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	case QE_CLK3:  val = QE_CMXGCR_USBCS_CLK3;  break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	case QE_CLK5:  val = QE_CMXGCR_USBCS_CLK5;  break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	case QE_CLK7:  val = QE_CMXGCR_USBCS_CLK7;  break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	case QE_CLK9:  val = QE_CMXGCR_USBCS_CLK9;  break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	case QE_CLK13: val = QE_CMXGCR_USBCS_CLK13; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	case QE_CLK17: val = QE_CMXGCR_USBCS_CLK17; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	case QE_CLK19: val = QE_CMXGCR_USBCS_CLK19; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	case QE_CLK21: val = QE_CMXGCR_USBCS_CLK21; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	case QE_BRG9:  val = QE_CMXGCR_USBCS_BRG9;  break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	case QE_BRG10: val = QE_CMXGCR_USBCS_BRG10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		pr_err("%s: requested unknown clock %d\n", __func__, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	if (qe_clock_is_brg(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		qe_setbrg(clk, rate, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	spin_lock_irqsave(&cmxgcr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	qe_clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	spin_unlock_irqrestore(&cmxgcr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) EXPORT_SYMBOL(qe_usb_clock_set);