^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/powerpc/sysdev/qe_lib/ucc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * QE UCC API Set - UCC specific routines implementations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Authors: Shlomi Gridish <gridish@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Li Yang <leoli@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <soc/fsl/qe/immap_qe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <soc/fsl/qe/qe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <soc/fsl/qe/ucc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UCC_TDM_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RX_SYNC_SHIFT_BASE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TX_SYNC_SHIFT_BASE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RX_CLK_SHIFT_BASE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TX_CLK_SHIFT_BASE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (ucc_num > UCC_MAX_NUM - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) spin_lock_irqsave(&cmxgcr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) spin_unlock_irqrestore(&cmxgcr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Configure the UCC to either Slow or Fast.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * A given UCC can be figured to support either "slow" devices (e.g. UART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * or "fast" devices (e.g. Ethernet).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 'ucc_num' is the UCC number, from 0 - 7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * must always be set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 __iomem *guemr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* The GUEMR register is at the same location for both slow and fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) devices, so we just use uccX.slow.guemr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) switch (ucc_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) case 0: guemr = &qe_immr->ucc1.slow.guemr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case 1: guemr = &qe_immr->ucc2.slow.guemr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 2: guemr = &qe_immr->ucc3.slow.guemr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) case 3: guemr = &qe_immr->ucc4.slow.guemr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case 4: guemr = &qe_immr->ucc5.slow.guemr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) case 5: guemr = &qe_immr->ucc6.slow.guemr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case 6: guemr = &qe_immr->ucc7.slow.guemr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 7: guemr = &qe_immr->ucc8.slow.guemr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) qe_clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) UCC_GUEMR_SET_RESERVED3 | speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void get_cmxucr_reg(unsigned int ucc_num, __be32 __iomem **cmxucr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int *reg_num, unsigned int *shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *reg_num = cmx + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *cmxucr = &qe_immr->qmx.cmxucr[cmx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *shift = 16 - 8 * (ucc_num & 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __be32 __iomem *cmxucr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* check if the UCC number is in range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ucc_num > UCC_MAX_NUM - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) qe_setbits_be32(cmxucr, mask << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) qe_clrbits_be32(cmxucr, mask << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum comm_dir mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __be32 __iomem *cmxucr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 clock_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* check if the UCC number is in range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ucc_num > UCC_MAX_NUM - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* The communications direction must be RX or TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) switch (reg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case QE_BRG1: clock_bits = 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case QE_BRG2: clock_bits = 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case QE_BRG7: clock_bits = 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case QE_BRG8: clock_bits = 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case QE_CLK9: clock_bits = 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case QE_CLK10: clock_bits = 6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case QE_CLK11: clock_bits = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case QE_CLK12: clock_bits = 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case QE_CLK15: clock_bits = 9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case QE_CLK16: clock_bits = 10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case QE_BRG5: clock_bits = 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case QE_BRG6: clock_bits = 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case QE_BRG7: clock_bits = 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case QE_BRG8: clock_bits = 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) case QE_CLK13: clock_bits = 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) case QE_CLK14: clock_bits = 6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case QE_CLK19: clock_bits = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case QE_CLK20: clock_bits = 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case QE_CLK15: clock_bits = 9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) case QE_CLK16: clock_bits = 10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case QE_BRG9: clock_bits = 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case QE_BRG10: clock_bits = 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case QE_BRG15: clock_bits = 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case QE_BRG16: clock_bits = 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) case QE_CLK3: clock_bits = 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case QE_CLK4: clock_bits = 6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case QE_CLK17: clock_bits = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case QE_CLK18: clock_bits = 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case QE_CLK7: clock_bits = 9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case QE_CLK8: clock_bits = 10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case QE_CLK16: clock_bits = 11; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case QE_BRG13: clock_bits = 1; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case QE_BRG14: clock_bits = 2; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case QE_BRG15: clock_bits = 3; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case QE_BRG16: clock_bits = 4; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case QE_CLK5: clock_bits = 5; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case QE_CLK6: clock_bits = 6; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case QE_CLK21: clock_bits = 7; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case QE_CLK22: clock_bits = 8; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case QE_CLK7: clock_bits = 9; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case QE_CLK8: clock_bits = 10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case QE_CLK16: clock_bits = 11; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) default: break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Check for invalid combination of clock and UCC number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!clock_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (mode == COMM_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) shift += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) qe_clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clock_bits << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int clock_bits = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * for TDM[0, 1, 2, 3], TX and RX use common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * clock source BRG3,4 and CLK1,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * for TDM[4, 5, 6, 7], TX and RX use common
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * clock source BRG12,13 and CLK23,24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) switch (tdm_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case QE_BRG3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) clock_bits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case QE_BRG4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) clock_bits = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case QE_CLK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) clock_bits = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case QE_CLK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) clock_bits = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case QE_BRG12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clock_bits = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case QE_BRG13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) clock_bits = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) case QE_CLK23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clock_bits = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case QE_CLK24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) clock_bits = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int clock_bits = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) switch (tdm_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case QE_CLK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case QE_CLK8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case QE_CLK5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case QE_CLK10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case QE_CLK7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case QE_CLK12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case QE_CLK9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case QE_CLK14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case QE_CLK11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case QE_CLK16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case QE_CLK13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case QE_CLK18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case QE_CLK15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case QE_CLK20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case QE_CLK17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case QE_CLK22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int ucc_get_tdm_tx_clk(u32 tdm_num, enum qe_clock clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int clock_bits = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) switch (tdm_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case QE_CLK4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case QE_CLK9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case QE_CLK6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case QE_CLK11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case QE_CLK8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case QE_CLK13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case QE_CLK10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case QE_CLK15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case QE_CLK12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case QE_CLK17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case QE_CLK14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case QE_CLK19:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case QE_CLK16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case QE_CLK21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case QE_CLK18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clock_bits = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) case QE_CLK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) clock_bits = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* tdm_num: TDM A-H port num is 0-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int ucc_get_tdm_rxtx_clk(enum comm_dir mode, u32 tdm_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) enum qe_clock clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) clock_bits = ucc_get_tdm_common_clk(tdm_num, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (clock_bits > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (mode == COMM_DIR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clock_bits = ucc_get_tdm_rx_clk(tdm_num, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (mode == COMM_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) clock_bits = ucc_get_tdm_tx_clk(tdm_num, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static u32 ucc_get_tdm_clk_shift(enum comm_dir mode, u32 tdm_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) shift = (mode == COMM_DIR_RX) ? RX_CLK_SHIFT_BASE : TX_CLK_SHIFT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (tdm_num < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) shift -= tdm_num * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) shift -= (tdm_num - 4) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) enum comm_dir mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int clock_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct qe_mux __iomem *qe_mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) __be32 __iomem *cmxs1cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) qe_mux_reg = &qe_immr->qmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (tdm_num > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* The communications direction must be RX or TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clock_bits = ucc_get_tdm_rxtx_clk(mode, tdm_num, clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (clock_bits < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) shift = ucc_get_tdm_clk_shift(mode, tdm_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) &qe_mux_reg->cmxsi1cr_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) qe_clrsetbits_be32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) clock_bits << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int ucc_get_tdm_sync_source(u32 tdm_num, enum qe_clock clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) enum comm_dir mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int source = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) source = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) source = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) switch (tdm_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case QE_BRG9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) source = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case QE_BRG10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) source = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case QE_BRG9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) source = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case QE_BRG11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) source = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case QE_BRG13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) source = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) case QE_BRG14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) source = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) switch (clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) case QE_BRG13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) source = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) case QE_BRG15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) source = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static u32 ucc_get_tdm_sync_shift(enum comm_dir mode, u32 tdm_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) shift = (mode == COMM_DIR_RX) ? RX_SYNC_SHIFT_BASE : TX_SYNC_SHIFT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) shift -= tdm_num * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) enum comm_dir mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct qe_mux __iomem *qe_mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) qe_mux_reg = &qe_immr->qmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (tdm_num >= UCC_TDM_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* The communications direction must be RX or TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (mode != COMM_DIR_RX && mode != COMM_DIR_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) source = ucc_get_tdm_sync_source(tdm_num, clock, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (source < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) shift = ucc_get_tdm_sync_shift(mode, tdm_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) QE_CMXUCR_TX_CLK_SRC_MASK << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) source << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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