^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * QUICC Engine GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) MontaVista Software, Inc. 2008.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* FIXME: needed for gpio_to_chip() get rid of this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <soc/fsl/qe/qe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct qe_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct of_mm_gpio_chip mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned long pin_flags[QE_PIO_PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QE_PIN_REQUESTED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* shadowed data register to clear/set bits safely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 cpdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* saved_regs used to restore dedicated functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct qe_pio_regs saved_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct qe_gpio_chip *qe_gc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) container_of(mm_gc, struct qe_gpio_chip, mm_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct qe_pio_regs __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) qe_gc->cpdata = qe_ioread32be(®s->cpdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) qe_gc->saved_regs.cpdata = qe_gc->cpdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) qe_gc->saved_regs.cpdir1 = qe_ioread32be(®s->cpdir1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) qe_gc->saved_regs.cpdir2 = qe_ioread32be(®s->cpdir2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) qe_gc->saved_regs.cppar1 = qe_ioread32be(®s->cppar1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) qe_gc->saved_regs.cppar2 = qe_ioread32be(®s->cppar2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) qe_gc->saved_regs.cpodr = qe_ioread32be(®s->cpodr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct qe_pio_regs __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return !!(qe_ioread32be(®s->cpdata) & pin_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct qe_pio_regs __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spin_lock_irqsave(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) qe_gc->cpdata |= pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) qe_gc->cpdata &= ~pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) spin_unlock_irqrestore(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void qe_gpio_set_multiple(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct qe_pio_regs __iomem *regs = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) spin_lock_irqsave(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (i = 0; i < gc->ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (*mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (__test_and_clear_bit(i, mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (test_bit(i, bits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spin_unlock_irqrestore(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) spin_lock_irqsave(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) spin_unlock_irqrestore(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) qe_gpio_set(gc, gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spin_lock_irqsave(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) spin_unlock_irqrestore(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct qe_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * The qe_gpio_chip name is unfortunate, we should change that to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * something like qe_pio_controller. Someday.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct qe_gpio_chip *controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * qe_pin_request - Request a QE pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @np: device node to get a pin from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @index: index of a pin in the device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Context: non-atomic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * This function return qe_pin so that you could use it with the rest of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * the QE Pin Multiplexing API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct qe_pin *qe_pin_request(struct device_node *np, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct qe_pin *qe_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct qe_gpio_chip *qe_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!qe_pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pr_debug("%s: can't allocate memory\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) err = of_get_gpio(np, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) gc = gpio_to_chip(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (WARN_ON(!gc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pr_debug("%s: tried to get a non-qe pin\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) qe_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) spin_lock_irqsave(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) err -= gc->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) qe_pin->controller = qe_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) qe_pin->num = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) spin_unlock_irqrestore(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return qe_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) kfree(qe_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pr_debug("%s failed with status %d\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EXPORT_SYMBOL(qe_pin_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * qe_pin_free - Free a pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @qe_pin: pointer to the qe_pin structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Context: any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * This function frees the qe_pin structure and makes a pin available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * for further qe_pin_request() calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) void qe_pin_free(struct qe_pin *qe_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct qe_gpio_chip *qe_gc = qe_pin->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) const int pin = qe_pin->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) spin_lock_irqsave(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) spin_unlock_irqrestore(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) kfree(qe_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) EXPORT_SYMBOL(qe_pin_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @qe_pin: pointer to the qe_pin structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Context: any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * This function resets a pin to a dedicated peripheral function that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * has been set up by the firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void qe_pin_set_dedicated(struct qe_pin *qe_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct qe_gpio_chip *qe_gc = qe_pin->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct qe_pio_regs *sregs = &qe_gc->saved_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int pin = qe_pin->num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) spin_lock_irqsave(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (second_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) qe_clrsetbits_be32(®s->cpdir2, mask2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) sregs->cpdir2 & mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) qe_clrsetbits_be32(®s->cppar2, mask2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) sregs->cppar2 & mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) qe_clrsetbits_be32(®s->cpdir1, mask2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) sregs->cpdir1 & mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) qe_clrsetbits_be32(®s->cppar1, mask2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) sregs->cppar1 & mask2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (sregs->cpdata & mask1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) qe_gc->cpdata |= mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) qe_gc->cpdata &= ~mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) spin_unlock_irqrestore(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) EXPORT_SYMBOL(qe_pin_set_dedicated);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * qe_pin_set_gpio - Set a pin to the GPIO mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @qe_pin: pointer to the qe_pin structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * Context: any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * This function sets a pin to the GPIO mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void qe_pin_set_gpio(struct qe_pin *qe_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct qe_gpio_chip *qe_gc = qe_pin->controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) spin_lock_irqsave(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Let's make it input by default, GPIO API is able to change that. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) spin_unlock_irqrestore(&qe_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) EXPORT_SYMBOL(qe_pin_set_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int __init qe_add_gpiochips(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct qe_gpio_chip *qe_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!qe_gc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) spin_lock_init(&qe_gc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mm_gc = &qe_gc->mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) gc = &mm_gc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mm_gc->save_regs = qe_gpio_save_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) gc->ngpio = QE_PIO_PINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) gc->direction_input = qe_gpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) gc->direction_output = qe_gpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) gc->get = qe_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) gc->set = qe_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) gc->set_multiple = qe_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pr_err("%pOF: registration failed with status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) np, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) kfree(qe_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* try others anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) arch_initcall(qe_add_gpiochips);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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