Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) menuconfig FSL_DPAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 	bool "QorIQ DPAA1 framework support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 	depends on ((FSL_SOC_BOOKE || ARCH_LAYERSCAPE) && ARCH_DMA_ADDR_T_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	select GENERIC_ALLOCATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	  The Freescale Data Path Acceleration Architecture (DPAA) is a set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	  hardware components on specific QorIQ multicore processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	  This architecture provides the infrastructure to support simplified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	  sharing of networking interfaces and accelerators by multiple CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	  The major h/w blocks composing DPAA are BMan and QMan.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	  The Buffer Manager (BMan) is a hardware buffer pool management block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	  that allows software and accelerators on the datapath to acquire and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	  release buffers in order to build frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	  The Queue Manager (QMan) is a hardware queue management block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	  that allows software and accelerators on the datapath to enqueue and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	  dequeue frames in order to communicate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) if FSL_DPAA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) config FSL_DPAA_CHECKING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	bool "Additional driver checking"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	  Compiles in additional checks, to sanity-check the drivers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	  any use of the exported API. Not recommended for performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) config FSL_BMAN_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	tristate "BMan self-tests"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	  Compile the BMan self-test code. These tests will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	  exercise the BMan APIs to confirm functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	  of both the software drivers and hardware device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) config FSL_BMAN_TEST_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	bool "High-level API self-test"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	depends on FSL_BMAN_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	  This requires the presence of cpu-affine portals, and performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	  high-level API testing with them (whichever portal(s) are affine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	  to the cpu(s) the test executes on).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) config FSL_QMAN_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	tristate "QMan self-tests"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	  Compile self-test code for QMan.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) config FSL_QMAN_TEST_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	bool "QMan high-level self-test"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	depends on FSL_QMAN_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	  This requires the presence of cpu-affine portals, and performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	  high-level API testing with them (whichever portal(s) are affine to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	  the cpu(s) the test executes on).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) config FSL_QMAN_TEST_STASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	bool "QMan 'hot potato' data-stashing self-test"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	depends on FSL_QMAN_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	  This performs a "hot potato" style test enqueuing/dequeuing a frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	  across a series of FQs scheduled to different portals (and cpus), with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	  DQRR, data and context stashing always on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) endif # FSL_DPAA