^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Broadcom STB SoCs Bus Unit Interface controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015, Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) "brcmstb: " KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/soc/brcmstb/brcmstb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RACENPREF_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RACPREFINST_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RACENINST_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RACPREFDATA_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RACENDATA_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RAC_CPU_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RACCFG_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DPREF_LINE_2_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DPREF_LINE_2_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RAC_DATA_INST_EN_MASK (1 << RACPREFINST_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) RACENPREF_MASK << RACENINST_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 1 << RACPREFDATA_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) RACENPREF_MASK << RACENDATA_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CPU_CREDIT_REG_MCPx_READ_CRED_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(x) ((x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(x) (((x) * 8) + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(x) ((x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static void __iomem *cpubiuctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static bool mcp_wr_pairing_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const int *cpubiuctrl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum cpubiuctrl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) CPU_CREDIT_REG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) CPU_MCP_FLOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CPU_WRITEBACK_CTRL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) RAC_CONFIG0_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) RAC_CONFIG1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) NUM_CPU_BIUCTRL_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline u32 cbc_readl(int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int offset = cpubiuctrl_regs[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (offset == -1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return (u32)-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return readl_relaxed(cpubiuctrl_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static inline void cbc_writel(u32 val, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int offset = cpubiuctrl_regs[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (offset == -1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(val, cpubiuctrl_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const int b15_cpubiuctrl_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [CPU_CREDIT_REG] = 0x184,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) [CPU_MCP_FLOW_REG] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [CPU_WRITEBACK_CTRL_REG] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [RAC_CONFIG0_REG] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [RAC_CONFIG1_REG] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Odd cases, e.g: 7260A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static const int b53_cpubiuctrl_no_wb_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) [CPU_CREDIT_REG] = 0x0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [CPU_MCP_FLOW_REG] = 0x0b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [CPU_WRITEBACK_CTRL_REG] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [RAC_CONFIG0_REG] = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [RAC_CONFIG1_REG] = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const int b53_cpubiuctrl_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) [CPU_CREDIT_REG] = 0x0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [CPU_MCP_FLOW_REG] = 0x0b4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [CPU_WRITEBACK_CTRL_REG] = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [RAC_CONFIG0_REG] = 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [RAC_CONFIG1_REG] = 0x7c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const int a72_cpubiuctrl_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [CPU_CREDIT_REG] = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [CPU_MCP_FLOW_REG] = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [CPU_WRITEBACK_CTRL_REG] = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [RAC_CONFIG0_REG] = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [RAC_CONFIG1_REG] = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int __init mcp_write_pairing_set(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 creds = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!cpubiuctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) creds = cbc_readl(CPU_CREDIT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (mcp_wr_pairing_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_info("MCP: Enabling write pairing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cbc_writel(creds | CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CPU_CREDIT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) } else if (creds & CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pr_info("MCP: Disabling write pairing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cbc_writel(creds & ~CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CPU_CREDIT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pr_info("MCP: Write pairing already disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const u32 a72_b53_mach_compat[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 0x7211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 0x7216,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 0x72164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 0x72165,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0x7255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 0x7260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 0x7268,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0x7271,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x7278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* The read-ahead cache present in the Brahma-B53 CPU is a special piece of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * hardware after the integrated L2 cache of the B53 CPU complex whose purpose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * is to prefetch instruction and/or data with a line size of either 64 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * or 256 bytes. The rationale is that the data-bus of the CPU interface is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * optimized for 256-byte transactions, and enabling the read-ahead cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * provides a significant performance boost (typically twice the performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * for a memcpy benchmark application).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * The read-ahead cache is transparent for Virtual Address cache maintenance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * operations: IC IVAU, DC IVAC, DC CVAC, DC CVAU and DC CIVAC. So no special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * handling is needed for the DMA API above and beyond what is included in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * arm64 implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * In addition, since the Point of Unification is typically between L1 and L2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * for the Brahma-B53 processor no special read-ahead cache handling is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * for the IC IALLU and IC IALLUIS cache maintenance operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * However, it is not possible to specify the cache level (L3) for the cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * maintenance instructions operating by set/way to operate on the read-ahead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * cache. The read-ahead cache will maintain coherency when inner cache lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * are cleaned by set/way, but if it is necessary to invalidate inner cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * lines by set/way to maintain coherency with system masters operating on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * shared memory that does not have hardware support for coherency, then it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * will also be necessary to explicitly invalidate the read-ahead cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void __init a72_b53_rac_enable_all(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 enable = 0, pref_dist, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pref_dist = cbc_readl(RAC_CONFIG1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) shift = cpu * RAC_CPU_SHIFT + RACPREFDATA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (cpubiuctrl_regs == a72_cpubiuctrl_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) enable &= ~(RACENPREF_MASK << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) enable |= 3 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cbc_writel(enable, RAC_CONFIG0_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cbc_writel(pref_dist, RAC_CONFIG1_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pr_info("%pOF: Broadcom %s read-ahead cache\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) np, cpubiuctrl_regs == a72_cpubiuctrl_regs ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "Cortex-A72" : "Brahma-B53");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void __init mcp_a72_b53_set(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) reg = brcmstb_get_family_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) for (i = 0; i < ARRAY_SIZE(a72_b53_mach_compat); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (BRCM_ID(reg) == a72_b53_mach_compat[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (i == ARRAY_SIZE(a72_b53_mach_compat))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Set all 3 MCP interfaces to 8 credits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) reg = cbc_readl(CPU_CREDIT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reg &= ~(CPU_CREDIT_REG_MCPx_WRITE_CRED_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) reg &= ~(CPU_CREDIT_REG_MCPx_READ_CRED_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) reg |= 8 << CPU_CREDIT_REG_MCPx_WRITE_CRED_SHIFT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg |= 8 << CPU_CREDIT_REG_MCPx_READ_CRED_SHIFT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) cbc_writel(reg, CPU_CREDIT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Max out the number of in-flight Jwords reads on the MCP interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) reg = cbc_readl(CPU_MCP_FLOW_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) reg |= CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CPU_MCP_FLOW_REG_MCPx_RDBUFF_CRED_SHIFT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) cbc_writel(reg, CPU_MCP_FLOW_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Enable writeback throttling, set timeout to 128 cycles, 256 cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * threshold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) reg = cbc_readl(CPU_WRITEBACK_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) reg |= CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) reg &= ~CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_THRESHOLD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) reg &= ~(CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) reg |= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) reg |= 7 << CPU_WRITEBACK_CTRL_REG_WB_THROTTLE_TIMEOUT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) cbc_writel(reg, CPU_WRITEBACK_CTRL_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int __init setup_hifcpubiuctrl_regs(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct device_node *cpu_dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 family_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) cpubiuctrl_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!cpubiuctrl_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pr_err("failed to remap BIU control base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cpu_dn = of_get_cpu_node(0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!cpu_dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pr_err("failed to obtain CPU device node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) cpubiuctrl_regs = b15_cpubiuctrl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) cpubiuctrl_regs = b53_cpubiuctrl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) else if (of_device_is_compatible(cpu_dn, "arm,cortex-a72"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) cpubiuctrl_regs = a72_cpubiuctrl_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pr_err("unsupported CPU\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) of_node_put(cpu_dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) family_id = brcmstb_get_family_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (BRCM_ID(family_id) == 0x7260 && BRCM_REV(family_id) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cpubiuctrl_regs = b53_cpubiuctrl_no_wb_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static u32 cpubiuctrl_reg_save[NUM_CPU_BIUCTRL_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int brcmstb_cpu_credit_reg_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!cpubiuctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) cpubiuctrl_reg_save[i] = cbc_readl(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static void brcmstb_cpu_credit_reg_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!cpubiuctrl_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (i = 0; i < NUM_CPU_BIUCTRL_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cbc_writel(cpubiuctrl_reg_save[i], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct syscore_ops brcmstb_cpu_credit_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .suspend = brcmstb_cpu_credit_reg_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .resume = brcmstb_cpu_credit_reg_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int __init brcmstb_biuctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* We might be running on a multi-platform kernel, don't make this a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * fatal error, just bail out early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = setup_hifcpubiuctrl_regs(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = mcp_write_pairing_set();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pr_err("MCP: Unable to disable write pairing!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) a72_b53_rac_enable_all(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mcp_a72_b53_set();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) register_syscore_ops(&brcmstb_cpu_credit_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) early_initcall(brcmstb_biuctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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