^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2015 Atmel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Alexandre Belloni <alexandre.belloni@free-electrons.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Boris Brezillon <boris.brezillon@free-electrons.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define pr_fmt(fmt) "AT91: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "soc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AT91_DBGU_CIDR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AT91_DBGU_EXID 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AT91_CHIPID_CIDR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AT91_CHIPID_EXID 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AT91_CIDR_VERSION(x) ((x) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AT91_CIDR_EXT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AT91_CIDR_MATCH_MASK 0x7fffffe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct at91_soc __initconst socs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifdef CONFIG_SOC_AT91RM9200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) AT91_SOC(AT91RM9200_CIDR_MATCH, 0, "at91rm9200 BGA", "at91rm9200"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifdef CONFIG_SOC_AT91SAM9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) AT91_SOC(AT91SAM9260_CIDR_MATCH, 0, "at91sam9260", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) AT91_SOC(AT91SAM9261_CIDR_MATCH, 0, "at91sam9261", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) AT91_SOC(AT91SAM9263_CIDR_MATCH, 0, "at91sam9263", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) AT91_SOC(AT91SAM9G20_CIDR_MATCH, 0, "at91sam9g20", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) AT91_SOC(AT91SAM9RL64_CIDR_MATCH, 0, "at91sam9rl64", NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M11_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "at91sam9m11", "at91sam9g45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9M10_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "at91sam9m10", "at91sam9g45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G46_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "at91sam9g46", "at91sam9g45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91SAM9G45_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "at91sam9g45", "at91sam9g45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G15_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "at91sam9g15", "at91sam9x5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G35_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "at91sam9g35", "at91sam9x5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X35_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "at91sam9x35", "at91sam9x5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9G25_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "at91sam9g25", "at91sam9x5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91SAM9X25_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "at91sam9x25", "at91sam9x5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN12_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "at91sam9cn12", "at91sam9n12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9N12_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "at91sam9n12", "at91sam9n12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91SAM9CN11_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "at91sam9cn11", "at91sam9n12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) AT91_SOC(AT91SAM9XE128_CIDR_MATCH, 0, "at91sam9xe128", "at91sam9xe128"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) AT91_SOC(AT91SAM9XE256_CIDR_MATCH, 0, "at91sam9xe256", "at91sam9xe256"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) AT91_SOC(AT91SAM9XE512_CIDR_MATCH, 0, "at91sam9xe512", "at91sam9xe512"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_SOC_SAM9X60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #ifdef CONFIG_SOC_SAMA5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "sama5d21", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D22CU_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "sama5d22", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D225C_D1M_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "sama5d225c 16MiB SiP", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D23CU_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "sama5d23", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CX_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "sama5d24", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D24CU_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "sama5d24", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D26CU_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "sama5d26", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CU_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "sama5d27", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27CN_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "sama5d27", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D1G_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "sama5d27c 128MiB SiP", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_D5M_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "sama5d27c 64MiB SiP", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD1G_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D27C_LD2G_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CU_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "sama5d28", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28CN_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "sama5d28", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_D1G_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "sama5d28c 128MiB SiP", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD1G_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D28C_LD2G_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D31_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "sama5d31", "sama5d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D33_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "sama5d33", "sama5d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D34_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "sama5d34", "sama5d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D35_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "sama5d35", "sama5d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) AT91_SOC(SAMA5D3_CIDR_MATCH, SAMA5D36_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "sama5d36", "sama5d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D41_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "sama5d41", "sama5d4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D42_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "sama5d42", "sama5d4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D43_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "sama5d43", "sama5d4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) AT91_SOC(SAMA5D4_CIDR_MATCH, SAMA5D44_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "sama5d44", "sama5d4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #ifdef CONFIG_SOC_SAMV7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) AT91_SOC(SAME70Q21_CIDR_MATCH, SAME70Q21_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) "same70q21", "same7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) AT91_SOC(SAME70Q20_CIDR_MATCH, SAME70Q20_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "same70q20", "same7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) AT91_SOC(SAME70Q19_CIDR_MATCH, SAME70Q19_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "same70q19", "same7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) AT91_SOC(SAMS70Q21_CIDR_MATCH, SAMS70Q21_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "sams70q21", "sams7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) AT91_SOC(SAMS70Q20_CIDR_MATCH, SAMS70Q20_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "sams70q20", "sams7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) AT91_SOC(SAMS70Q19_CIDR_MATCH, SAMS70Q19_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) "sams70q19", "sams7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) AT91_SOC(SAMV71Q21_CIDR_MATCH, SAMV71Q21_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "samv71q21", "samv7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) AT91_SOC(SAMV71Q20_CIDR_MATCH, SAMV71Q20_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "samv71q20", "samv7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) AT91_SOC(SAMV71Q19_CIDR_MATCH, SAMV71Q19_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "samv71q19", "samv7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) AT91_SOC(SAMV70Q20_CIDR_MATCH, SAMV70Q20_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "samv70q20", "samv7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) AT91_SOC(SAMV70Q19_CIDR_MATCH, SAMV70Q19_EXID_MATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) "samv70q19", "samv7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "atmel,at91sam9260-dbgu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) regs = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pr_warn("Could not map DBGU iomem range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *cidr = readl(regs + AT91_DBGU_CIDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) *exid = readl(regs + AT91_DBGU_EXID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-chipid");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) regs = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_warn("Could not map DBGU iomem range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) *cidr = readl(regs + AT91_CHIPID_CIDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *exid = readl(regs + AT91_CHIPID_EXID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct soc_device_attribute *soc_dev_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) const struct at91_soc *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct soc_device *soc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 cidr, exid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * in the dbgu device but in the chipid device whose purpose is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * to expose these two registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pr_warn("Could not find identification node");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (soc = socs; soc->name; soc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (soc->cidr_match != (cidr & AT91_CIDR_MATCH_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!soc->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pr_warn("Could not find matching SoC description\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!soc_dev_attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) soc_dev_attr->family = soc->family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) soc_dev_attr->soc_id = soc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) AT91_CIDR_VERSION(cidr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) soc_dev = soc_device_register(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (IS_ERR(soc_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) kfree(soc_dev_attr->revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) kfree(soc_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pr_warn("Could not register SoC device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (soc->family)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pr_info("Detected SoC family: %s\n", soc->family);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_info("Detected SoC: %s, revision %X\n", soc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) AT91_CIDR_VERSION(cidr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return soc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct of_device_id at91_soc_allowed_list[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .compatible = "atmel,at91rm9200", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { .compatible = "atmel,at91sam9", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .compatible = "atmel,sama5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .compatible = "atmel,samv7", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int __init atmel_soc_device_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct device_node *np = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!of_match_node(at91_soc_allowed_list, np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) at91_soc_init(socs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) subsys_initcall(atmel_soc_device_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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