Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2019 Google Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * modify it under the terms of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * as published by the Free Software Foundation; either version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * 2 of the License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Provides a simple driver to control the ASPEED P2A interface which allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * the host to read and write to various regions of the BMC's memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/aspeed-p2a-ctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DEVICE_NAME	"aspeed-p2a-ctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* SCU2C is a Misc. Control Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SCU2C 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* SCU180 is the PCIe Configuration Setting Control Register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SCU180 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Bit 1 controls the P2A bridge, while bit 0 controls the entire VGA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * on the PCI bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SCU180_ENP2A BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* The ast2400/2500 both have six ranges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define P2A_REGION_COUNT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u64 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct aspeed_p2a_model_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* min, max, bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct region regions[P2A_REGION_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct aspeed_p2a_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct miscdevice miscdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	const struct aspeed_p2a_model_data *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* Access to these needs to be locked, held via probe, mapping ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	 * and release, remove.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct mutex tracking;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u32 readers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u32 readerwriters[P2A_REGION_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	phys_addr_t mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	resource_size_t mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct aspeed_p2a_user {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct file *file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct aspeed_p2a_ctrl *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	/* The entire memory space is opened for reading once the bridge is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 * enabled, therefore this needs only to be tracked once per user.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	 * If any user has it open for read, the bridge must stay enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u32 read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* Each entry of the array corresponds to a P2A Region.  If the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 * opens for read or readwrite, the reference goes up here.  On
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * release, this array is walked and references adjusted accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32 readwrite[P2A_REGION_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static void aspeed_p2a_enable_bridge(struct aspeed_p2a_ctrl *p2a_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	regmap_update_bits(p2a_ctrl->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		SCU180, SCU180_ENP2A, SCU180_ENP2A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static void aspeed_p2a_disable_bridge(struct aspeed_p2a_ctrl *p2a_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	regmap_update_bits(p2a_ctrl->regmap, SCU180, SCU180_ENP2A, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int aspeed_p2a_mmap(struct file *file, struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned long vsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	pgprot_t prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct aspeed_p2a_user *priv = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct aspeed_p2a_ctrl *ctrl = priv->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (ctrl->mem_base == 0 && ctrl->mem_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	vsize = vma->vm_end - vma->vm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	prot = vma->vm_page_prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (vma->vm_pgoff + vma_pages(vma) > ctrl->mem_size >> PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* ast2400/2500 AHB accesses are not cache coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	prot = pgprot_noncached(prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (remap_pfn_range(vma, vma->vm_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		(ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		vsize, prot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static bool aspeed_p2a_region_acquire(struct aspeed_p2a_user *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		struct aspeed_p2a_ctrl *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		struct aspeed_p2a_ctrl_mapping *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u64 base, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	bool matched = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	base = map->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	end = map->addr + (map->length - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* If the value is a legal u32, it will find a match. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	for (i = 0; i < P2A_REGION_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		const struct region *curr = &ctrl->config->regions[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		/* If the top of this region is lower than your base, skip it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		if (curr->max < base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		/* If the bottom of this region is higher than your end, bail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (curr->min > end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		/* Lock this and update it, therefore it someone else is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		 * closing their file out, this'll preserve the increment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		mutex_lock(&ctrl->tracking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		ctrl->readerwriters[i] += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		mutex_unlock(&ctrl->tracking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		/* Track with the user, so when they close their file, we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		 * decrement properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		priv->readwrite[i] += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		/* Enable the region as read-write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		regmap_update_bits(ctrl->regmap, SCU2C, curr->bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		matched = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return matched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static long aspeed_p2a_ioctl(struct file *file, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct aspeed_p2a_user *priv = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct aspeed_p2a_ctrl *ctrl = priv->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	void __user *arg = (void __user *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct aspeed_p2a_ctrl_mapping map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (copy_from_user(&map, arg, sizeof(map)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case ASPEED_P2A_CTRL_IOCTL_SET_WINDOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		/* If they want a region to be read-only, since the entire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		 * region is read-only once enabled, we just need to track this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		 * user wants to read from the bridge, and if it's not enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		 * Enable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		if (map.flags == ASPEED_P2A_CTRL_READ_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			mutex_lock(&ctrl->tracking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			ctrl->readers += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			mutex_unlock(&ctrl->tracking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			/* Track with the user, so when they close their file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			 * we can decrement properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			priv->read += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		} else if (map.flags == ASPEED_P2A_CTRL_READWRITE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			/* If we don't acquire any region return error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			if (!aspeed_p2a_region_acquire(priv, ctrl, &map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			/* Invalid map flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		aspeed_p2a_enable_bridge(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	case ASPEED_P2A_CTRL_IOCTL_GET_MEMORY_CONFIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		/* This is a request for the memory-region and corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		 * length that is used by the driver for mmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		map.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		map.addr = ctrl->mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		map.length = ctrl->mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return copy_to_user(arg, &map, sizeof(map)) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * When a user opens this file, we create a structure to track their mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * A user can map a region as read-only (bridge enabled), or read-write (bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  * flipped, and bridge enabled).  Either way, this tracking is used, s.t. when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * they release the device references are handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * The bridge is not enabled until a user calls an ioctl to map a region,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * simply opening the device does not enable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int aspeed_p2a_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct aspeed_p2a_user *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	priv = kmalloc(sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	priv->file = file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	priv->read = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	memset(priv->readwrite, 0, sizeof(priv->readwrite));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* The file's private_data is initialized to the p2a_ctrl. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	priv->parent = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Set the file's private_data to the user's data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	file->private_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  * This will close the users mappings.  It will go through what they had opened
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)  * for readwrite, and decrement those counts.  If at the end, this is the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * user, it'll close the bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int aspeed_p2a_release(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	u32 bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	bool open_regions = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct aspeed_p2a_user *priv = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	/* Lock others from changing these values until everything is updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 * in one pass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	mutex_lock(&priv->parent->tracking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	priv->parent->readers -= priv->read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	for (i = 0; i < P2A_REGION_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		priv->parent->readerwriters[i] -= priv->readwrite[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		if (priv->parent->readerwriters[i] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			open_regions = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			bits |= priv->parent->config->regions[i].bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/* Setting a bit to 1 disables the region, so let's just OR with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	 * above to disable any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	/* Note, if another user is trying to ioctl, they can't grab tracking,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 * and therefore can't grab either register mutex.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 * If another user is trying to close, they can't grab tracking either.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	regmap_update_bits(priv->parent->regmap, SCU2C, bits, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* If parent->readers is zero and open windows is 0, disable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 * bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (!open_regions && priv->parent->readers == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		aspeed_p2a_disable_bridge(priv->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	mutex_unlock(&priv->parent->tracking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct file_operations aspeed_p2a_ctrl_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.mmap = aspeed_p2a_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.unlocked_ioctl = aspeed_p2a_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.open = aspeed_p2a_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.release = aspeed_p2a_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* The regions are controlled by SCU2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static void aspeed_p2a_disable_all(struct aspeed_p2a_ctrl *p2a_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	u32 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	for (i = 0; i < P2A_REGION_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		value |= p2a_ctrl->config->regions[i].bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	regmap_update_bits(p2a_ctrl->regmap, SCU2C, value, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	/* Disable the bridge. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	aspeed_p2a_disable_bridge(p2a_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int aspeed_p2a_ctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct aspeed_p2a_ctrl *misc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct resource resm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	misc_ctrl = devm_kzalloc(dev, sizeof(*misc_ctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (!misc_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	mutex_init(&misc_ctrl->tracking);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	/* optional. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	node = of_parse_phandle(dev->of_node, "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		rc = of_address_to_resource(node, 0, &resm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			dev_err(dev, "Couldn't address to resource for reserved memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		misc_ctrl->mem_size = resource_size(&resm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		misc_ctrl->mem_base = resm.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	misc_ctrl->regmap = syscon_node_to_regmap(pdev->dev.parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (IS_ERR(misc_ctrl->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		dev_err(dev, "Couldn't get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	misc_ctrl->config = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	dev_set_drvdata(&pdev->dev, misc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	aspeed_p2a_disable_all(misc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	misc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	misc_ctrl->miscdev.name = DEVICE_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	misc_ctrl->miscdev.fops = &aspeed_p2a_ctrl_fops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	misc_ctrl->miscdev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	rc = misc_register(&misc_ctrl->miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		dev_err(dev, "Unable to register device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int aspeed_p2a_ctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	struct aspeed_p2a_ctrl *p2a_ctrl = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	misc_deregister(&p2a_ctrl->miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SCU2C_DRAM	BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SCU2C_SPI	BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SCU2C_SOC	BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SCU2C_FLASH	BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct aspeed_p2a_model_data ast2400_model_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.regions = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		{0x00000000, 0x17FFFFFF, SCU2C_FLASH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		{0x18000000, 0x1FFFFFFF, SCU2C_SOC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		{0x20000000, 0x2FFFFFFF, SCU2C_FLASH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		{0x30000000, 0x3FFFFFFF, SCU2C_SPI},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		{0x40000000, 0x5FFFFFFF, SCU2C_DRAM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		{0x60000000, 0xFFFFFFFF, SCU2C_SOC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const struct aspeed_p2a_model_data ast2500_model_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.regions = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		{0x00000000, 0x0FFFFFFF, SCU2C_FLASH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		{0x10000000, 0x1FFFFFFF, SCU2C_SOC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		{0x20000000, 0x3FFFFFFF, SCU2C_FLASH},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		{0x40000000, 0x5FFFFFFF, SCU2C_SOC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		{0x60000000, 0x7FFFFFFF, SCU2C_SPI},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		{0x80000000, 0xFFFFFFFF, SCU2C_DRAM},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct of_device_id aspeed_p2a_ctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	{ .compatible = "aspeed,ast2400-p2a-ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	  .data = &ast2400_model_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	{ .compatible = "aspeed,ast2500-p2a-ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	  .data = &ast2500_model_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct platform_driver aspeed_p2a_ctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		.name		= DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		.of_match_table = aspeed_p2a_ctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.probe = aspeed_p2a_ctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	.remove = aspeed_p2a_ctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) module_platform_driver(aspeed_p2a_ctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MODULE_DEVICE_TABLE(of, aspeed_p2a_ctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MODULE_AUTHOR("Patrick Venture <venture@google.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MODULE_DESCRIPTION("Control for aspeed 2400/2500 P2A VGA HOST to BMC mappings");