^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017 IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/miscdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/poll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/aspeed-lpc-ctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DEVICE_NAME "aspeed-lpc-ctrl"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HICR5 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HICR5_ENL2H BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HICR5_ENFWH BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HICR7 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HICR8 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct aspeed_lpc_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct miscdevice miscdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) phys_addr_t mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) resource_size_t mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 pnor_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 pnor_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct aspeed_lpc_ctrl *file_aspeed_lpc_ctrl(struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return container_of(file->private_data, struct aspeed_lpc_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int aspeed_lpc_ctrl_mmap(struct file *file, struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long vsize = vma->vm_end - vma->vm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pgprot_t prot = vma->vm_page_prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (vma->vm_pgoff + vma_pages(vma) > lpc_ctrl->mem_size >> PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* ast2400/2500 AHB accesses are not cache coherent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) prot = pgprot_noncached(prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (remap_pfn_range(vma, vma->vm_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) (lpc_ctrl->mem_base >> PAGE_SHIFT) + vma->vm_pgoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) vsize, prot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct aspeed_lpc_ctrl *lpc_ctrl = file_aspeed_lpc_ctrl(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device *dev = file->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void __user *p = (void __user *)param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct aspeed_lpc_ctrl_mapping map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) long rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (copy_from_user(&map, p, sizeof(map)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (map.flags != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case ASPEED_LPC_CTRL_IOCTL_GET_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* The flash windows don't report their size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (map.window_type != ASPEED_LPC_CTRL_WINDOW_MEMORY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Support more than one window id in the future */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (map.window_id != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* If memory-region is not described in device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!lpc_ctrl->mem_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_dbg(dev, "Didn't find reserved memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) map.size = lpc_ctrl->mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return copy_to_user(p, &map, sizeof(map)) ? -EFAULT : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) case ASPEED_LPC_CTRL_IOCTL_MAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * The top half of HICR7 is the MSB of the BMC address of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * The bottom half of HICR7 is the MSB of the HOST LPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * firmware space address of the mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * The 1 bits in the top of half of HICR8 represent the bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * (in the requested address) that should be ignored and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * replaced with those from the top half of HICR7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * The 1 bits in the bottom half of HICR8 represent the bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * (in the requested address) that should be kept and pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * into the BMC address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * It doesn't make sense to talk about a size or offset with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * low 16 bits set. Both HICR7 and HICR8 talk about the top 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * bits of addresses and sizes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if ((map.size & 0x0000ffff) || (map.offset & 0x0000ffff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Because of the way the masks work in HICR8 offset has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * be a multiple of size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (map.offset & (map.size - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (map.window_type == ASPEED_LPC_CTRL_WINDOW_FLASH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!lpc_ctrl->pnor_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_dbg(dev, "Didn't find host pnor flash\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) addr = lpc_ctrl->pnor_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) size = lpc_ctrl->pnor_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } else if (map.window_type == ASPEED_LPC_CTRL_WINDOW_MEMORY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* If memory-region is not described in device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!lpc_ctrl->mem_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_dbg(dev, "Didn't find reserved memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) addr = lpc_ctrl->mem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) size = lpc_ctrl->mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Check overflow first! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (map.offset + map.size < map.offset ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) map.offset + map.size > size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (map.size == 0 || map.size > size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) addr += map.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * addr (host lpc address) is safe regardless of values. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * simply changes the address the host has to request on its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * side of the LPC bus. This cannot impact the hosts own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * memory space by surprise as LPC specific accessors are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * required. The only strange thing that could be done is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * setting the lower 16 bits but the shift takes care of that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) rc = regmap_write(lpc_ctrl->regmap, HICR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (addr | (map.addr >> 16)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rc = regmap_write(lpc_ctrl->regmap, HICR8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (~(map.size - 1)) | ((map.size >> 16) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * Enable LPC FHW cycles. This is required for the host to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * access the regions specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return regmap_update_bits(lpc_ctrl->regmap, HICR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) HICR5_ENFWH | HICR5_ENL2H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) HICR5_ENFWH | HICR5_ENL2H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct file_operations aspeed_lpc_ctrl_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .mmap = aspeed_lpc_ctrl_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .unlocked_ioctl = aspeed_lpc_ctrl_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int aspeed_lpc_ctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct aspeed_lpc_ctrl *lpc_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct resource resm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) lpc_ctrl = devm_kzalloc(dev, sizeof(*lpc_ctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!lpc_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* If flash is described in device tree then store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) node = of_parse_phandle(dev->of_node, "flash", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_dbg(dev, "Didn't find host pnor flash node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rc = of_address_to_resource(node, 1, &resm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(dev, "Couldn't address to resource for flash\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) lpc_ctrl->pnor_size = resource_size(&resm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) lpc_ctrl->pnor_base = resm.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_set_drvdata(&pdev->dev, lpc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* If memory-region is described in device tree then store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) node = of_parse_phandle(dev->of_node, "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_dbg(dev, "Didn't find reserved memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rc = of_address_to_resource(node, 0, &resm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dev, "Couldn't address to resource for reserved memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) lpc_ctrl->mem_size = resource_size(&resm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) lpc_ctrl->mem_base = resm.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) lpc_ctrl->regmap = syscon_node_to_regmap(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pdev->dev.parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (IS_ERR(lpc_ctrl->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(dev, "Couldn't get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) lpc_ctrl->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (IS_ERR(lpc_ctrl->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return dev_err_probe(dev, PTR_ERR(lpc_ctrl->clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "couldn't get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) rc = clk_prepare_enable(lpc_ctrl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(dev, "couldn't enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) lpc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) lpc_ctrl->miscdev.name = DEVICE_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) lpc_ctrl->miscdev.fops = &aspeed_lpc_ctrl_fops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) lpc_ctrl->miscdev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) rc = misc_register(&lpc_ctrl->miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_err(dev, "Unable to register device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) clk_disable_unprepare(lpc_ctrl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int aspeed_lpc_ctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct aspeed_lpc_ctrl *lpc_ctrl = dev_get_drvdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) misc_deregister(&lpc_ctrl->miscdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) clk_disable_unprepare(lpc_ctrl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct of_device_id aspeed_lpc_ctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { .compatible = "aspeed,ast2400-lpc-ctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { .compatible = "aspeed,ast2500-lpc-ctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static struct platform_driver aspeed_lpc_ctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = DEVICE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .of_match_table = aspeed_lpc_ctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .probe = aspeed_lpc_ctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .remove = aspeed_lpc_ctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) module_platform_driver(aspeed_lpc_ctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_DEVICE_TABLE(of, aspeed_lpc_ctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_AUTHOR("Cyril Bur <cyrilbur@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MODULE_DESCRIPTION("Control for aspeed 2400/2500 LPC HOST to BMC mappings");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags