Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (c) 2017 BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* AO Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AO_RTI_GEN_PWR_SLEEP0		(0x3a << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define GEN_PWR_VPU_HDMI		BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define GEN_PWR_VPU_HDMI_ISO		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) /* HHI Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define HHI_MEM_PD_REG0			(0x40 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HHI_VPU_MEM_PD_REG0		(0x41 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HHI_VPU_MEM_PD_REG1		(0x42 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HHI_VPU_MEM_PD_REG2		(0x4d << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct meson_gx_pwrc_vpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct generic_pm_domain genpd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct regmap *regmap_ao;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct regmap *regmap_hhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct clk *vpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct clk *vapb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return container_of(d, struct meson_gx_pwrc_vpu, genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 			   GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/* Power Down Memories */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 				   0x3 << i, 0x3 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 				   0x3 << i, 0x3 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	for (i = 8; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				   BIT(i), BIT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			   GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	clk_disable_unprepare(pd->vpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	clk_disable_unprepare(pd->vapb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int meson_g12a_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			   GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/* Power Down Memories */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				   0x3 << i, 0x3 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 				   0x3 << i, 0x3 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				   0x3 << i, 0x3 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	for (i = 8; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 				   BIT(i), BIT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			   GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	clk_disable_unprepare(pd->vpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	clk_disable_unprepare(pd->vapb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	ret = clk_prepare_enable(pd->vpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ret = clk_prepare_enable(pd->vapb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		clk_disable_unprepare(pd->vpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			   GEN_PWR_VPU_HDMI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* Power Up Memories */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 				   0x3 << i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				   0x3 << i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	for (i = 8; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 				   BIT(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	ret = reset_control_assert(pd->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			   GEN_PWR_VPU_HDMI_ISO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ret = reset_control_deassert(pd->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	ret = meson_gx_pwrc_vpu_setup_clk(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int meson_g12a_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			   GEN_PWR_VPU_HDMI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* Power Up Memories */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 				   0x3 << i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				   0x3 << i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	for (i = 0; i < 32; i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				   0x3 << i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	for (i = 8; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				   BIT(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ret = reset_control_assert(pd->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			   GEN_PWR_VPU_HDMI_ISO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	ret = reset_control_deassert(pd->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	ret = meson_gx_pwrc_vpu_setup_clk(pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return (reg & GEN_PWR_VPU_HDMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct meson_gx_pwrc_vpu vpu_hdmi_pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.genpd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.name = "vpu_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.power_off = meson_gx_pwrc_vpu_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.power_on = meson_gx_pwrc_vpu_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct meson_gx_pwrc_vpu vpu_hdmi_pd_g12a = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.genpd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.name = "vpu_hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.power_off = meson_g12a_pwrc_vpu_power_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.power_on = meson_g12a_pwrc_vpu_power_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	const struct meson_gx_pwrc_vpu *vpu_pd_match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct regmap *regmap_ao, *regmap_hhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct meson_gx_pwrc_vpu *vpu_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct clk *vpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct clk *vapb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	bool powered_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	vpu_pd_match = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (!vpu_pd_match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		dev_err(&pdev->dev, "failed to get match data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	vpu_pd = devm_kzalloc(&pdev->dev, sizeof(*vpu_pd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (!vpu_pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	memcpy(vpu_pd, vpu_pd_match, sizeof(*vpu_pd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	regmap_ao = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (IS_ERR(regmap_ao)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		dev_err(&pdev->dev, "failed to get regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return PTR_ERR(regmap_ao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 						     "amlogic,hhi-sysctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (IS_ERR(regmap_hhi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		dev_err(&pdev->dev, "failed to get HHI regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return PTR_ERR(regmap_hhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	rstc = devm_reset_control_array_get(&pdev->dev, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (IS_ERR(rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		if (PTR_ERR(rstc) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			dev_err(&pdev->dev, "failed to get reset lines\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		return PTR_ERR(rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	vpu_clk = devm_clk_get(&pdev->dev, "vpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (IS_ERR(vpu_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		dev_err(&pdev->dev, "vpu clock request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		return PTR_ERR(vpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	vapb_clk = devm_clk_get(&pdev->dev, "vapb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (IS_ERR(vapb_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		dev_err(&pdev->dev, "vapb clock request failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return PTR_ERR(vapb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	vpu_pd->regmap_ao = regmap_ao;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	vpu_pd->regmap_hhi = regmap_hhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	vpu_pd->rstc = rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	vpu_pd->vpu_clk = vpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	vpu_pd->vapb_clk = vapb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	platform_set_drvdata(pdev, vpu_pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* If already powered, sync the clock states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	if (!powered_off) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		ret = meson_gx_pwrc_vpu_setup_clk(vpu_pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	vpu_pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	pm_genpd_init(&vpu_pd->genpd, NULL, powered_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	return of_genpd_add_provider_simple(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 					    &vpu_pd->genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	struct meson_gx_pwrc_vpu *vpu_pd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	bool powered_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if (!powered_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		vpu_pd->genpd.power_off(&vpu_pd->genpd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	{ .compatible = "amlogic,meson-gx-pwrc-vpu", .data = &vpu_hdmi_pd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	  .compatible = "amlogic,meson-g12a-pwrc-vpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	  .data = &vpu_hdmi_pd_g12a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_DEVICE_TABLE(of, meson_gx_pwrc_vpu_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct platform_driver meson_gx_pwrc_vpu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.probe	= meson_gx_pwrc_vpu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.shutdown = meson_gx_pwrc_vpu_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.name		= "meson_gx_pwrc_vpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.of_match_table	= meson_gx_pwrc_vpu_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) module_platform_driver(meson_gx_pwrc_vpu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MODULE_LICENSE("GPL v2");