Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2019 BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <dt-bindings/power/meson8-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <dt-bindings/power/meson-axg-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <dt-bindings/power/meson-g12a-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <dt-bindings/power/meson-gxbb-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <dt-bindings/power/meson-sm1-power.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* AO Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GX_AO_RTI_GEN_PWR_SLEEP0	(0x3a << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GX_AO_RTI_GEN_PWR_ISO0		(0x3b << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * Meson8/Meson8b/Meson8m2 only expose the power management registers of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * AO-bus as syscon. 0x3a from GX translates to 0x02, 0x3b translates to 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MESON8_AO_RTI_GEN_PWR_SLEEP0	(0x02 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MESON8_AO_RTI_GEN_PWR_ISO0	(0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* HHI Offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define HHI_MEM_PD_REG0			(0x40 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define HHI_VPU_MEM_PD_REG0		(0x41 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define HHI_VPU_MEM_PD_REG1		(0x42 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define HHI_VPU_MEM_PD_REG3		(0x43 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define HHI_VPU_MEM_PD_REG4		(0x44 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define HHI_AUDIO_MEM_PD_REG0		(0x45 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define HHI_NANOQ_MEM_PD_REG0		(0x46 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define HHI_NANOQ_MEM_PD_REG1		(0x47 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define HHI_VPU_MEM_PD_REG2		(0x4d << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct meson_ee_pwrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct meson_ee_pwrc_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct meson_ee_pwrc_mem_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct meson_ee_pwrc_top_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	unsigned int sleep_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned int sleep_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	unsigned int iso_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int iso_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct meson_ee_pwrc_domain_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned int reset_names_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	unsigned int clk_names_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct meson_ee_pwrc_top_domain *top_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int mem_pd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct meson_ee_pwrc_mem_domain *mem_pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	bool (*get_power)(struct meson_ee_pwrc_domain *pwrc_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) struct meson_ee_pwrc_domain_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct meson_ee_pwrc_domain_desc *domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* TOP Power Domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static struct meson_ee_pwrc_top_domain gx_pwrc_vpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.sleep_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.iso_reg = GX_AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.iso_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) static struct meson_ee_pwrc_top_domain meson8_pwrc_vpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.sleep_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.sleep_mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.iso_reg = MESON8_AO_RTI_GEN_PWR_SLEEP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.iso_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define SM1_EE_PD(__bit)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, 		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.sleep_mask = BIT(__bit), 			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.iso_reg = GX_AO_RTI_GEN_PWR_ISO0, 		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.iso_mask = BIT(__bit), 			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Memory PD Domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VPU_MEMPD(__reg)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{ __reg, GENMASK(1, 0) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{ __reg, GENMASK(3, 2) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{ __reg, GENMASK(5, 4) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	{ __reg, GENMASK(7, 6) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{ __reg, GENMASK(9, 8) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{ __reg, GENMASK(11, 10) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{ __reg, GENMASK(13, 12) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{ __reg, GENMASK(15, 14) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{ __reg, GENMASK(17, 16) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ __reg, GENMASK(19, 18) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{ __reg, GENMASK(21, 20) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ __reg, GENMASK(23, 22) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ __reg, GENMASK(25, 24) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ __reg, GENMASK(27, 26) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ __reg, GENMASK(29, 28) },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ __reg, GENMASK(31, 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VPU_HHI_MEMPD(__reg)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ __reg, BIT(8) },					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ __reg, BIT(9) },					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ __reg, BIT(10) },					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ __reg, BIT(11) },					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{ __reg, BIT(12) },					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{ __reg, BIT(13) },					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{ __reg, BIT(14) },					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{ __reg, BIT(15) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_vpu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct meson_ee_pwrc_mem_domain gxbb_pwrc_mem_vpu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct meson_ee_pwrc_mem_domain meson_pwrc_mem_eth[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ HHI_MEM_PD_REG0, GENMASK(3, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct meson_ee_pwrc_mem_domain meson8_pwrc_audio_dsp_mem[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{ HHI_MEM_PD_REG0, GENMASK(1, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct meson_ee_pwrc_mem_domain meson8_pwrc_mem_vpu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	{ HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	{ HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	{ HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	{ HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	{ HHI_NANOQ_MEM_PD_REG0, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	{ HHI_NANOQ_MEM_PD_REG1, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{ HHI_MEM_PD_REG0, GENMASK(31, 30) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	{ HHI_MEM_PD_REG0, GENMASK(29, 26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ HHI_MEM_PD_REG0, GENMASK(25, 18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct meson_ee_pwrc_mem_domain axg_pwrc_mem_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ HHI_MEM_PD_REG0, GENMASK(5, 4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	{ HHI_MEM_PD_REG0, GENMASK(5, 4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	{ HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.name = __name,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.reset_names_count = __resets,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.clk_names_count = __clks,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.top_pd = __top_pd,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.mem_pd_count = ARRAY_SIZE(__mem),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.mem_pd = __mem,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.get_power = __get_power,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TOP_PD(__name, __top_pd, __mem, __get_power)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.name = __name,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.top_pd = __top_pd,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.mem_pd_count = ARRAY_SIZE(__mem),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.mem_pd = __mem,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.get_power = __get_power,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MEM_PD(__name, __mem)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	TOP_PD(__name, NULL, __mem, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct meson_ee_pwrc_domain_desc axg_pwrc_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	[PWRC_AXG_VPU_ID]  = VPU_PD("VPU", &gx_pwrc_vpu, axg_pwrc_mem_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				     pwrc_ee_get_power, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	[PWRC_AXG_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	[PWRC_AXG_AUDIO_ID] = MEM_PD("AUDIO", axg_pwrc_mem_audio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	[PWRC_G12A_VPU_ID]  = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				     pwrc_ee_get_power, 11, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	[PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	[PWRC_GXBB_VPU_ID]  = VPU_PD("VPU", &gx_pwrc_vpu, gxbb_pwrc_mem_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				     pwrc_ee_get_power, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	[PWRC_GXBB_ETHERNET_MEM_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static struct meson_ee_pwrc_domain_desc meson8_pwrc_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	[PWRC_MESON8_VPU_ID]  = VPU_PD("VPU", &meson8_pwrc_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				       meson8_pwrc_mem_vpu, pwrc_ee_get_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				       0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	[PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 					       meson_pwrc_mem_eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	[PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 						meson8_pwrc_audio_dsp_mem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct meson_ee_pwrc_domain_desc meson8b_pwrc_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	[PWRC_MESON8_VPU_ID]  = VPU_PD("VPU", &meson8_pwrc_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				       meson8_pwrc_mem_vpu, pwrc_ee_get_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 				       11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	[PWRC_MESON8_ETHERNET_MEM_ID] = MEM_PD("ETHERNET_MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 					       meson_pwrc_mem_eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	[PWRC_MESON8_AUDIO_DSP_MEM_ID] = MEM_PD("AUDIO_DSP_MEM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 						meson8_pwrc_audio_dsp_mem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	[PWRC_SM1_VPU_ID]  = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 				    pwrc_ee_get_power, 11, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	[PWRC_SM1_NNA_ID]  = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				    pwrc_ee_get_power),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	[PWRC_SM1_USB_ID]  = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				    pwrc_ee_get_power),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	[PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				    pwrc_ee_get_power),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	[PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				    pwrc_ee_get_power),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	[PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	[PWRC_SM1_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct meson_ee_pwrc_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct generic_pm_domain base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	bool enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct meson_ee_pwrc *pwrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct meson_ee_pwrc_domain_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int num_rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct meson_ee_pwrc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	struct regmap *regmap_ao;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	struct regmap *regmap_hhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	struct meson_ee_pwrc_domain *domains;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct genpd_onecell_data xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static bool pwrc_ee_get_power(struct meson_ee_pwrc_domain *pwrc_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	regmap_read(pwrc_domain->pwrc->regmap_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		    pwrc_domain->desc.top_pd->sleep_reg, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	return (reg & pwrc_domain->desc.top_pd->sleep_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int meson_ee_pwrc_off(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct meson_ee_pwrc_domain *pwrc_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		container_of(domain, struct meson_ee_pwrc_domain, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (pwrc_domain->desc.top_pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 				   pwrc_domain->desc.top_pd->sleep_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 				   pwrc_domain->desc.top_pd->sleep_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				   pwrc_domain->desc.top_pd->sleep_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 				   pwrc_domain->desc.mem_pd[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 				   pwrc_domain->desc.mem_pd[i].mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				   pwrc_domain->desc.mem_pd[i].mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	if (pwrc_domain->desc.top_pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				   pwrc_domain->desc.top_pd->iso_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 				   pwrc_domain->desc.top_pd->iso_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				   pwrc_domain->desc.top_pd->iso_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (pwrc_domain->num_clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		clk_bulk_disable_unprepare(pwrc_domain->num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 					   pwrc_domain->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int meson_ee_pwrc_on(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct meson_ee_pwrc_domain *pwrc_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		container_of(domain, struct meson_ee_pwrc_domain, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (pwrc_domain->desc.top_pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 				   pwrc_domain->desc.top_pd->sleep_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 				   pwrc_domain->desc.top_pd->sleep_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	for (i = 0 ; i < pwrc_domain->desc.mem_pd_count ; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		regmap_update_bits(pwrc_domain->pwrc->regmap_hhi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 				   pwrc_domain->desc.mem_pd[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 				   pwrc_domain->desc.mem_pd[i].mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	udelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	ret = reset_control_assert(pwrc_domain->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (pwrc_domain->desc.top_pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		regmap_update_bits(pwrc_domain->pwrc->regmap_ao,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 				   pwrc_domain->desc.top_pd->iso_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 				   pwrc_domain->desc.top_pd->iso_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	ret = reset_control_deassert(pwrc_domain->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	return clk_bulk_prepare_enable(pwrc_domain->num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 				       pwrc_domain->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int meson_ee_pwrc_init_domain(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 				     struct meson_ee_pwrc *pwrc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 				     struct meson_ee_pwrc_domain *dom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	dom->pwrc = pwrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	dom->num_rstc = dom->desc.reset_names_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	dom->num_clks = dom->desc.clk_names_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	if (dom->num_rstc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		int count = reset_control_get_count(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		if (count != dom->num_rstc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			dev_warn(&pdev->dev, "Invalid resets count %d for domain %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 				 count, dom->desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		dom->rstc = devm_reset_control_array_get(&pdev->dev, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 							 false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		if (IS_ERR(dom->rstc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			return PTR_ERR(dom->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	if (dom->num_clks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		int ret = devm_clk_bulk_get_all(&pdev->dev, &dom->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		if (dom->num_clks != ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 			dev_warn(&pdev->dev, "Invalid clocks count %d for domain %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 				 ret, dom->desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 			dom->num_clks = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	dom->base.name = dom->desc.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	dom->base.power_on = meson_ee_pwrc_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	dom->base.power_off = meson_ee_pwrc_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)          * TOFIX: This is a special case for the VPU power domain, which can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	 * be enabled previously by the bootloader. In this case the VPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)          * pipeline may be functional but no driver maybe never attach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)          * to this power domain, and if the domain is disabled it could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)          * cause system errors. This is why the pm_domain_always_on_gov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)          * is used here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)          * For the same reason, the clocks should be enabled in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)          * we need to power the domain off, otherwise the internal clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)          * prepare/enable counters won't be in sync.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)          */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (dom->num_clks && dom->desc.get_power && !dom->desc.get_power(dom)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		dom->base.flags = GENPD_FLAG_ALWAYS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		ret = pm_genpd_init(&dom->base, NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		ret = pm_genpd_init(&dom->base, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 				    (dom->desc.get_power ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 				     dom->desc.get_power(dom) : true));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int meson_ee_pwrc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	const struct meson_ee_pwrc_domain_data *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	struct regmap *regmap_ao, *regmap_hhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	struct meson_ee_pwrc *pwrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	match = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		dev_err(&pdev->dev, "failed to get match data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	pwrc = devm_kzalloc(&pdev->dev, sizeof(*pwrc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	if (!pwrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	pwrc->xlate.domains = devm_kcalloc(&pdev->dev, match->count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 					   sizeof(*pwrc->xlate.domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 					   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	if (!pwrc->xlate.domains)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	pwrc->domains = devm_kcalloc(&pdev->dev, match->count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 				     sizeof(*pwrc->domains), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	if (!pwrc->domains)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	pwrc->xlate.num_domains = match->count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	regmap_hhi = syscon_node_to_regmap(of_get_parent(pdev->dev.of_node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	if (IS_ERR(regmap_hhi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		dev_err(&pdev->dev, "failed to get HHI regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		return PTR_ERR(regmap_hhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	regmap_ao = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 						    "amlogic,ao-sysctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	if (IS_ERR(regmap_ao)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		dev_err(&pdev->dev, "failed to get AO regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		return PTR_ERR(regmap_ao);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	pwrc->regmap_ao = regmap_ao;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	pwrc->regmap_hhi = regmap_hhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	platform_set_drvdata(pdev, pwrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	for (i = 0 ; i < match->count ; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		struct meson_ee_pwrc_domain *dom = &pwrc->domains[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 		memcpy(&dom->desc, &match->domains[i], sizeof(dom->desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		ret = meson_ee_pwrc_init_domain(pdev, pwrc, dom);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		pwrc->xlate.domains[i] = &dom->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static void meson_ee_pwrc_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	struct meson_ee_pwrc *pwrc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	for (i = 0 ; i < pwrc->xlate.num_domains ; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		struct meson_ee_pwrc_domain *dom = &pwrc->domains[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		if (dom->desc.get_power && !dom->desc.get_power(dom))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 			meson_ee_pwrc_off(&dom->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	.count = ARRAY_SIZE(g12a_pwrc_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	.domains = g12a_pwrc_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static struct meson_ee_pwrc_domain_data meson_ee_axg_pwrc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	.count = ARRAY_SIZE(axg_pwrc_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	.domains = axg_pwrc_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static struct meson_ee_pwrc_domain_data meson_ee_gxbb_pwrc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	.count = ARRAY_SIZE(gxbb_pwrc_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	.domains = gxbb_pwrc_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static struct meson_ee_pwrc_domain_data meson_ee_m8_pwrc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	.count = ARRAY_SIZE(meson8_pwrc_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	.domains = meson8_pwrc_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static struct meson_ee_pwrc_domain_data meson_ee_m8b_pwrc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	.count = ARRAY_SIZE(meson8b_pwrc_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	.domains = meson8b_pwrc_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	.count = ARRAY_SIZE(sm1_pwrc_domains),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	.domains = sm1_pwrc_domains,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const struct of_device_id meson_ee_pwrc_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 		.compatible = "amlogic,meson8-pwrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 		.data = &meson_ee_m8_pwrc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 		.compatible = "amlogic,meson8b-pwrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		.data = &meson_ee_m8b_pwrc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 		.compatible = "amlogic,meson8m2-pwrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		.data = &meson_ee_m8b_pwrc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 		.compatible = "amlogic,meson-axg-pwrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 		.data = &meson_ee_axg_pwrc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 		.compatible = "amlogic,meson-gxbb-pwrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 		.data = &meson_ee_gxbb_pwrc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 		.compatible = "amlogic,meson-g12a-pwrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 		.data = &meson_ee_g12a_pwrc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		.compatible = "amlogic,meson-sm1-pwrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 		.data = &meson_ee_sm1_pwrc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_DEVICE_TABLE(of, meson_ee_pwrc_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static struct platform_driver meson_ee_pwrc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	.probe = meson_ee_pwrc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 	.shutdown = meson_ee_pwrc_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 		.name		= "meson_ee_pwrc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		.of_match_table	= meson_ee_pwrc_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) module_platform_driver(meson_ee_pwrc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MODULE_LICENSE("GPL v2");