^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Neil Armstrong <narmstrong@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static DEFINE_MUTEX(measure_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MSR_CLK_DUTY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MSR_CLK_REG0 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MSR_CLK_REG1 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MSR_CLK_REG2 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MSR_DURATION GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MSR_ENABLE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MSR_CONT BIT(17) /* continuous measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MSR_INTR BIT(18) /* interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MSR_RUN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MSR_CLK_SRC GENMASK(26, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MSR_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MSR_VAL_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DIV_MIN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DIV_STEP 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DIV_MAX 640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_MSR_MAX 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct meson_msr_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct meson_msr *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct meson_msr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct meson_msr_id msr_table[CLK_MSR_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_MSR_ID(__id, __name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [__id] = {.id = __id, .name = __name,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) CLK_MSR_ID(0, "ring_osc_out_ee0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CLK_MSR_ID(1, "ring_osc_out_ee1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CLK_MSR_ID(2, "ring_osc_out_ee2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) CLK_MSR_ID(3, "a9_ring_osck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CLK_MSR_ID(6, "vid_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) CLK_MSR_ID(7, "clk81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CLK_MSR_ID(8, "encp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CLK_MSR_ID(9, "encl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) CLK_MSR_ID(11, "eth_rmii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) CLK_MSR_ID(13, "amclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CLK_MSR_ID(14, "fec_clk_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CLK_MSR_ID(15, "fec_clk_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CLK_MSR_ID(16, "fec_clk_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CLK_MSR_ID(18, "a9_clk_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CLK_MSR_ID(19, "hdmi_sys"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CLK_MSR_ID(20, "rtc_osc_clk_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CLK_MSR_ID(21, "i2s_clk_in_src0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CLK_MSR_ID(22, "clk_rmii_from_pad"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CLK_MSR_ID(23, "hdmi_ch0_tmds"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CLK_MSR_ID(24, "lvds_fifo"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_MSR_ID(26, "sc_clk_int"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) CLK_MSR_ID(28, "sar_adc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) CLK_MSR_ID(30, "mpll_clk_test_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) CLK_MSR_ID(31, "audac_clkpi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) CLK_MSR_ID(32, "vdac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) CLK_MSR_ID(33, "sdhc_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) CLK_MSR_ID(34, "sdhc_sd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) CLK_MSR_ID(35, "mali"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CLK_MSR_ID(36, "hdmi_tx_pixel"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) CLK_MSR_ID(38, "vdin_meas"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) CLK_MSR_ID(39, "pcm_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) CLK_MSR_ID(40, "pcm_mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CLK_MSR_ID(41, "eth_rx_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) CLK_MSR_ID(42, "pwm_d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) CLK_MSR_ID(43, "pwm_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) CLK_MSR_ID(44, "pwm_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) CLK_MSR_ID(45, "pwm_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CLK_MSR_ID(46, "pcm2_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) CLK_MSR_ID(47, "ddr_dpll_pt"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) CLK_MSR_ID(48, "pwm_f"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CLK_MSR_ID(49, "pwm_e"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CLK_MSR_ID(59, "hcodec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) CLK_MSR_ID(60, "usb_32k_alt"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) CLK_MSR_ID(61, "gpio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) CLK_MSR_ID(62, "vid2_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CLK_MSR_ID(63, "mipi_csi_cfg"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) CLK_MSR_ID(0, "ring_osc_out_ee_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) CLK_MSR_ID(1, "ring_osc_out_ee_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CLK_MSR_ID(2, "ring_osc_out_ee_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) CLK_MSR_ID(3, "a53_ring_osc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) CLK_MSR_ID(4, "gp0_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) CLK_MSR_ID(6, "enci"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) CLK_MSR_ID(7, "clk81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CLK_MSR_ID(8, "encp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CLK_MSR_ID(9, "encl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CLK_MSR_ID(10, "vdac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CLK_MSR_ID(11, "rgmii_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CLK_MSR_ID(12, "pdm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CLK_MSR_ID(13, "amclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CLK_MSR_ID(14, "fec_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) CLK_MSR_ID(15, "fec_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) CLK_MSR_ID(16, "fec_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) CLK_MSR_ID(17, "sys_pll_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CLK_MSR_ID(18, "sys_cpu_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CLK_MSR_ID(19, "hdmitx_sys"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CLK_MSR_ID(20, "rtc_osc_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CLK_MSR_ID(21, "i2s_in_src0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CLK_MSR_ID(22, "eth_phy_ref"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CLK_MSR_ID(23, "hdmi_todig"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CLK_MSR_ID(26, "sc_int"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) CLK_MSR_ID(28, "sar_adc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CLK_MSR_ID(31, "mpll_test_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CLK_MSR_ID(32, "vdec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CLK_MSR_ID(35, "mali"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CLK_MSR_ID(36, "hdmi_tx_pixel"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) CLK_MSR_ID(37, "i958"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) CLK_MSR_ID(38, "vdin_meas"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) CLK_MSR_ID(39, "pcm_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CLK_MSR_ID(40, "pcm_mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CLK_MSR_ID(41, "eth_rx_or_rmii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CLK_MSR_ID(42, "mp0_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CLK_MSR_ID(43, "fclk_div5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CLK_MSR_ID(44, "pwm_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLK_MSR_ID(45, "pwm_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CLK_MSR_ID(46, "vpu"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CLK_MSR_ID(47, "ddr_dpll_pt"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CLK_MSR_ID(48, "mp1_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CLK_MSR_ID(49, "mp2_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CLK_MSR_ID(50, "mp3_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CLK_MSR_ID(51, "nand_core"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CLK_MSR_ID(52, "sd_emmc_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_MSR_ID(53, "sd_emmc_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CLK_MSR_ID(55, "vid_pll_div_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CLK_MSR_ID(56, "cci"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CLK_MSR_ID(57, "wave420l_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CLK_MSR_ID(58, "wave420l_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CLK_MSR_ID(59, "hcodec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CLK_MSR_ID(60, "alt_32k"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CLK_MSR_ID(61, "gpio_msr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CLK_MSR_ID(62, "hevc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CLK_MSR_ID(66, "vid_lock"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CLK_MSR_ID(70, "pwm_f"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CLK_MSR_ID(71, "pwm_e"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CLK_MSR_ID(72, "pwm_d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CLK_MSR_ID(73, "pwm_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CLK_MSR_ID(75, "aoclkx2_int"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CLK_MSR_ID(76, "aoclk_int"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CLK_MSR_ID(77, "rng_ring_osc_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CLK_MSR_ID(78, "rng_ring_osc_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CLK_MSR_ID(79, "rng_ring_osc_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CLK_MSR_ID(80, "rng_ring_osc_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CLK_MSR_ID(81, "vapb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CLK_MSR_ID(82, "ge2d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct meson_msr_id clk_msr_axg[CLK_MSR_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CLK_MSR_ID(0, "ring_osc_out_ee_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CLK_MSR_ID(1, "ring_osc_out_ee_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CLK_MSR_ID(2, "ring_osc_out_ee_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CLK_MSR_ID(3, "a53_ring_osc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CLK_MSR_ID(4, "gp0_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CLK_MSR_ID(5, "gp1_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CLK_MSR_ID(7, "clk81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CLK_MSR_ID(9, "encl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) CLK_MSR_ID(17, "sys_pll_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CLK_MSR_ID(18, "sys_cpu_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) CLK_MSR_ID(20, "rtc_osc_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CLK_MSR_ID(23, "mmc_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) CLK_MSR_ID(28, "sar_adc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) CLK_MSR_ID(31, "mpll_test_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CLK_MSR_ID(40, "mod_eth_tx_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) CLK_MSR_ID(41, "mod_eth_rx_clk_rmii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) CLK_MSR_ID(42, "mp0_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CLK_MSR_ID(43, "fclk_div5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) CLK_MSR_ID(44, "pwm_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CLK_MSR_ID(45, "pwm_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) CLK_MSR_ID(46, "vpu"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CLK_MSR_ID(47, "ddr_dpll_pt"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CLK_MSR_ID(48, "mp1_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CLK_MSR_ID(49, "mp2_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CLK_MSR_ID(50, "mp3_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CLK_MSR_ID(51, "sd_emmm_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CLK_MSR_ID(52, "sd_emmc_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CLK_MSR_ID(61, "gpio_msr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CLK_MSR_ID(66, "audio_slv_lrclk_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CLK_MSR_ID(67, "audio_slv_lrclk_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CLK_MSR_ID(68, "audio_slv_lrclk_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CLK_MSR_ID(69, "audio_slv_sclk_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CLK_MSR_ID(70, "audio_slv_sclk_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) CLK_MSR_ID(71, "audio_slv_sclk_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CLK_MSR_ID(72, "pwm_d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CLK_MSR_ID(73, "pwm_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CLK_MSR_ID(74, "wifi_beacon"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CLK_MSR_ID(75, "tdmin_lb_lrcl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CLK_MSR_ID(76, "tdmin_lb_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CLK_MSR_ID(77, "rng_ring_osc_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) CLK_MSR_ID(78, "rng_ring_osc_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CLK_MSR_ID(79, "rng_ring_osc_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CLK_MSR_ID(80, "rng_ring_osc_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CLK_MSR_ID(81, "vapb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CLK_MSR_ID(82, "ge2d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CLK_MSR_ID(84, "audio_resample"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) CLK_MSR_ID(85, "audio_pdm_sys"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) CLK_MSR_ID(86, "audio_spdifout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) CLK_MSR_ID(87, "audio_spdifin"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) CLK_MSR_ID(88, "audio_lrclk_f"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) CLK_MSR_ID(89, "audio_lrclk_e"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CLK_MSR_ID(90, "audio_lrclk_d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CLK_MSR_ID(91, "audio_lrclk_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CLK_MSR_ID(92, "audio_lrclk_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CLK_MSR_ID(93, "audio_lrclk_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CLK_MSR_ID(94, "audio_sclk_f"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CLK_MSR_ID(95, "audio_sclk_e"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CLK_MSR_ID(96, "audio_sclk_d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CLK_MSR_ID(97, "audio_sclk_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CLK_MSR_ID(98, "audio_sclk_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CLK_MSR_ID(99, "audio_sclk_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CLK_MSR_ID(100, "audio_mclk_f"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CLK_MSR_ID(101, "audio_mclk_e"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CLK_MSR_ID(102, "audio_mclk_d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CLK_MSR_ID(103, "audio_mclk_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CLK_MSR_ID(104, "audio_mclk_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) CLK_MSR_ID(105, "audio_mclk_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CLK_MSR_ID(106, "pcie_refclk_n"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CLK_MSR_ID(107, "pcie_refclk_p"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CLK_MSR_ID(108, "audio_locker_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) CLK_MSR_ID(109, "audio_locker_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct meson_msr_id clk_msr_g12a[CLK_MSR_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) CLK_MSR_ID(0, "ring_osc_out_ee_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CLK_MSR_ID(1, "ring_osc_out_ee_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) CLK_MSR_ID(2, "ring_osc_out_ee_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) CLK_MSR_ID(3, "sys_cpu_ring_osc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) CLK_MSR_ID(4, "gp0_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) CLK_MSR_ID(6, "enci"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) CLK_MSR_ID(7, "clk81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CLK_MSR_ID(8, "encp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) CLK_MSR_ID(9, "encl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CLK_MSR_ID(10, "vdac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CLK_MSR_ID(11, "eth_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CLK_MSR_ID(12, "hifi_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) CLK_MSR_ID(13, "mod_tcon"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CLK_MSR_ID(14, "fec_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CLK_MSR_ID(15, "fec_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CLK_MSR_ID(16, "fec_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) CLK_MSR_ID(17, "sys_pll_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) CLK_MSR_ID(18, "sys_cpu_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) CLK_MSR_ID(19, "lcd_an_ph2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) CLK_MSR_ID(20, "rtc_osc_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) CLK_MSR_ID(21, "lcd_an_ph3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) CLK_MSR_ID(22, "eth_phy_ref"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) CLK_MSR_ID(23, "mpll_50m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CLK_MSR_ID(24, "eth_125m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) CLK_MSR_ID(25, "eth_rmii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) CLK_MSR_ID(26, "sc_int"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) CLK_MSR_ID(27, "in_mac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) CLK_MSR_ID(28, "sar_adc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) CLK_MSR_ID(29, "pcie_inp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) CLK_MSR_ID(30, "pcie_inn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) CLK_MSR_ID(31, "mpll_test_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CLK_MSR_ID(32, "vdec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) CLK_MSR_ID(33, "sys_cpu_ring_osc_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) CLK_MSR_ID(34, "eth_mpll_50m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) CLK_MSR_ID(35, "mali"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) CLK_MSR_ID(36, "hdmi_tx_pixel"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) CLK_MSR_ID(37, "cdac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) CLK_MSR_ID(38, "vdin_meas"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) CLK_MSR_ID(39, "bt656"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CLK_MSR_ID(41, "eth_rx_or_rmii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) CLK_MSR_ID(42, "mp0_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CLK_MSR_ID(43, "fclk_div5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) CLK_MSR_ID(44, "pwm_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) CLK_MSR_ID(45, "pwm_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) CLK_MSR_ID(46, "vpu"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CLK_MSR_ID(47, "ddr_dpll_pt"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) CLK_MSR_ID(48, "mp1_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) CLK_MSR_ID(49, "mp2_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CLK_MSR_ID(50, "mp3_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) CLK_MSR_ID(51, "sd_emmc_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) CLK_MSR_ID(52, "sd_emmc_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) CLK_MSR_ID(53, "sd_emmc_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) CLK_MSR_ID(54, "vpu_clkc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) CLK_MSR_ID(55, "vid_pll_div_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) CLK_MSR_ID(56, "wave420l_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CLK_MSR_ID(57, "wave420l_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CLK_MSR_ID(58, "wave420l_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CLK_MSR_ID(59, "hcodec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CLK_MSR_ID(61, "gpio_msr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) CLK_MSR_ID(62, "hevcb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CLK_MSR_ID(63, "dsi_meas"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CLK_MSR_ID(64, "spicc_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) CLK_MSR_ID(65, "spicc_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) CLK_MSR_ID(66, "vid_lock"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) CLK_MSR_ID(67, "dsi_phy"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) CLK_MSR_ID(68, "hdcp22_esm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) CLK_MSR_ID(69, "hdcp22_skp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) CLK_MSR_ID(70, "pwm_f"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) CLK_MSR_ID(71, "pwm_e"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) CLK_MSR_ID(72, "pwm_d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CLK_MSR_ID(73, "pwm_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) CLK_MSR_ID(75, "hevcf"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) CLK_MSR_ID(77, "rng_ring_osc_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) CLK_MSR_ID(78, "rng_ring_osc_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) CLK_MSR_ID(79, "rng_ring_osc_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) CLK_MSR_ID(80, "rng_ring_osc_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) CLK_MSR_ID(81, "vapb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) CLK_MSR_ID(82, "ge2d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CLK_MSR_ID(83, "co_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) CLK_MSR_ID(84, "co_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CLK_MSR_ID(89, "hdmi_todig"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) CLK_MSR_ID(90, "hdmitx_sys"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) CLK_MSR_ID(91, "sys_cpub_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CLK_MSR_ID(92, "sys_pll_cpub_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) CLK_MSR_ID(94, "eth_phy_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CLK_MSR_ID(95, "eth_phy_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) CLK_MSR_ID(96, "vpu_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) CLK_MSR_ID(97, "cpu_b_tmp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) CLK_MSR_ID(98, "ts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) CLK_MSR_ID(99, "ring_osc_out_ee_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) CLK_MSR_ID(100, "ring_osc_out_ee_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) CLK_MSR_ID(101, "ring_osc_out_ee_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CLK_MSR_ID(102, "ring_osc_out_ee_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) CLK_MSR_ID(103, "ring_osc_out_ee_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) CLK_MSR_ID(104, "ring_osc_out_ee_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) CLK_MSR_ID(105, "ring_osc_out_ee_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CLK_MSR_ID(106, "ephy_test"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) CLK_MSR_ID(107, "au_dac_g128x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CLK_MSR_ID(108, "audio_locker_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) CLK_MSR_ID(109, "audio_locker_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) CLK_MSR_ID(110, "audio_tdmout_c_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) CLK_MSR_ID(111, "audio_tdmout_b_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CLK_MSR_ID(112, "audio_tdmout_a_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) CLK_MSR_ID(113, "audio_tdmin_lb_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CLK_MSR_ID(114, "audio_tdmin_c_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) CLK_MSR_ID(115, "audio_tdmin_b_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) CLK_MSR_ID(116, "audio_tdmin_a_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) CLK_MSR_ID(117, "audio_resample"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) CLK_MSR_ID(118, "audio_pdm_sys"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) CLK_MSR_ID(119, "audio_spdifout_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) CLK_MSR_ID(120, "audio_spdifout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) CLK_MSR_ID(121, "audio_spdifin"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) CLK_MSR_ID(122, "audio_pdm_dclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct meson_msr_id clk_msr_sm1[CLK_MSR_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) CLK_MSR_ID(0, "ring_osc_out_ee_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CLK_MSR_ID(1, "ring_osc_out_ee_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) CLK_MSR_ID(2, "ring_osc_out_ee_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) CLK_MSR_ID(3, "ring_osc_out_ee_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) CLK_MSR_ID(4, "gp0_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) CLK_MSR_ID(5, "gp1_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CLK_MSR_ID(6, "enci"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) CLK_MSR_ID(7, "clk81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) CLK_MSR_ID(8, "encp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) CLK_MSR_ID(9, "encl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) CLK_MSR_ID(10, "vdac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) CLK_MSR_ID(11, "eth_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CLK_MSR_ID(12, "hifi_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) CLK_MSR_ID(13, "mod_tcon"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) CLK_MSR_ID(14, "fec_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) CLK_MSR_ID(15, "fec_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) CLK_MSR_ID(16, "fec_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) CLK_MSR_ID(17, "sys_pll_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) CLK_MSR_ID(18, "sys_cpu_div16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CLK_MSR_ID(19, "lcd_an_ph2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) CLK_MSR_ID(20, "rtc_osc_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) CLK_MSR_ID(21, "lcd_an_ph3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) CLK_MSR_ID(22, "eth_phy_ref"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) CLK_MSR_ID(23, "mpll_50m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) CLK_MSR_ID(24, "eth_125m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) CLK_MSR_ID(25, "eth_rmii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CLK_MSR_ID(26, "sc_int"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CLK_MSR_ID(27, "in_mac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CLK_MSR_ID(28, "sar_adc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) CLK_MSR_ID(29, "pcie_inp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) CLK_MSR_ID(30, "pcie_inn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) CLK_MSR_ID(31, "mpll_test_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) CLK_MSR_ID(32, "vdec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CLK_MSR_ID(34, "eth_mpll_50m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CLK_MSR_ID(35, "mali"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) CLK_MSR_ID(36, "hdmi_tx_pixel"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) CLK_MSR_ID(37, "cdac"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) CLK_MSR_ID(38, "vdin_meas"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) CLK_MSR_ID(39, "bt656"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) CLK_MSR_ID(40, "arm_ring_osc_out_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) CLK_MSR_ID(41, "eth_rx_or_rmii"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) CLK_MSR_ID(42, "mp0_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CLK_MSR_ID(43, "fclk_div5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CLK_MSR_ID(44, "pwm_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) CLK_MSR_ID(45, "pwm_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) CLK_MSR_ID(46, "vpu"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CLK_MSR_ID(47, "ddr_dpll_pt"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) CLK_MSR_ID(48, "mp1_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) CLK_MSR_ID(49, "mp2_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) CLK_MSR_ID(50, "mp3_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) CLK_MSR_ID(51, "sd_emmc_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) CLK_MSR_ID(52, "sd_emmc_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) CLK_MSR_ID(53, "sd_emmc_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) CLK_MSR_ID(54, "vpu_clkc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) CLK_MSR_ID(55, "vid_pll_div_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) CLK_MSR_ID(56, "wave420l_a"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) CLK_MSR_ID(57, "wave420l_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) CLK_MSR_ID(58, "wave420l_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) CLK_MSR_ID(59, "hcodec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CLK_MSR_ID(60, "arm_ring_osc_out_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) CLK_MSR_ID(61, "gpio_msr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CLK_MSR_ID(62, "hevcb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) CLK_MSR_ID(63, "dsi_meas"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) CLK_MSR_ID(64, "spicc_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CLK_MSR_ID(65, "spicc_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) CLK_MSR_ID(66, "vid_lock"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) CLK_MSR_ID(67, "dsi_phy"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) CLK_MSR_ID(68, "hdcp22_esm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) CLK_MSR_ID(69, "hdcp22_skp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) CLK_MSR_ID(70, "pwm_f"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CLK_MSR_ID(71, "pwm_e"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CLK_MSR_ID(72, "pwm_d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) CLK_MSR_ID(73, "pwm_c"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) CLK_MSR_ID(74, "arm_ring_osc_out_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) CLK_MSR_ID(75, "hevcf"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) CLK_MSR_ID(76, "arm_ring_osc_out_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CLK_MSR_ID(77, "rng_ring_osc_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) CLK_MSR_ID(78, "rng_ring_osc_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) CLK_MSR_ID(79, "rng_ring_osc_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) CLK_MSR_ID(80, "rng_ring_osc_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CLK_MSR_ID(81, "vapb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) CLK_MSR_ID(82, "ge2d"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CLK_MSR_ID(83, "co_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) CLK_MSR_ID(84, "co_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) CLK_MSR_ID(85, "arm_ring_osc_out_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) CLK_MSR_ID(86, "arm_ring_osc_out_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) CLK_MSR_ID(87, "mipi_dsi_phy"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) CLK_MSR_ID(88, "cis2_adapt"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) CLK_MSR_ID(89, "hdmi_todig"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) CLK_MSR_ID(90, "hdmitx_sys"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) CLK_MSR_ID(91, "nna_core"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CLK_MSR_ID(92, "nna_axi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) CLK_MSR_ID(93, "vad"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) CLK_MSR_ID(94, "eth_phy_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CLK_MSR_ID(95, "eth_phy_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) CLK_MSR_ID(96, "vpu_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) CLK_MSR_ID(97, "cpu_b_tmp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) CLK_MSR_ID(98, "ts"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) CLK_MSR_ID(99, "arm_ring_osc_out_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) CLK_MSR_ID(100, "arm_ring_osc_out_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) CLK_MSR_ID(101, "arm_ring_osc_out_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) CLK_MSR_ID(102, "arm_ring_osc_out_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) CLK_MSR_ID(103, "arm_ring_osc_out_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) CLK_MSR_ID(104, "arm_ring_osc_out_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) CLK_MSR_ID(105, "arm_ring_osc_out_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) CLK_MSR_ID(106, "ephy_test"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) CLK_MSR_ID(107, "au_dac_g128x"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) CLK_MSR_ID(108, "audio_locker_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) CLK_MSR_ID(109, "audio_locker_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) CLK_MSR_ID(110, "audio_tdmout_c_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CLK_MSR_ID(111, "audio_tdmout_b_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) CLK_MSR_ID(112, "audio_tdmout_a_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) CLK_MSR_ID(113, "audio_tdmin_lb_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) CLK_MSR_ID(114, "audio_tdmin_c_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) CLK_MSR_ID(115, "audio_tdmin_b_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) CLK_MSR_ID(116, "audio_tdmin_a_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) CLK_MSR_ID(117, "audio_resample"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) CLK_MSR_ID(118, "audio_pdm_sys"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) CLK_MSR_ID(119, "audio_spdifout_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) CLK_MSR_ID(120, "audio_spdifout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) CLK_MSR_ID(121, "audio_spdifin"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) CLK_MSR_ID(122, "audio_pdm_dclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) CLK_MSR_ID(123, "audio_resampled"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) CLK_MSR_ID(124, "earcrx_pll"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) CLK_MSR_ID(125, "earcrx_pll_test"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) CLK_MSR_ID(126, "csi_phy0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) CLK_MSR_ID(127, "csi2_data"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int meson_measure_id(struct meson_msr_id *clk_msr_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned int duration)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct meson_msr *priv = clk_msr_id->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = mutex_lock_interruptible(&measure_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) regmap_write(priv->regmap, MSR_CLK_REG0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Set measurement duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_DURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) FIELD_PREP(MSR_DURATION, duration - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Set ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_CLK_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) FIELD_PREP(MSR_CLK_SRC, clk_msr_id->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Enable & Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) regmap_update_bits(priv->regmap, MSR_CLK_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MSR_RUN | MSR_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MSR_RUN | MSR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) val, !(val & MSR_BUSY), 10, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) mutex_unlock(&measure_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Get the value in multiple of gate time counts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) regmap_read(priv->regmap, MSR_CLK_REG2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mutex_unlock(&measure_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (val >= MSR_VAL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return DIV_ROUND_CLOSEST_ULL((val & MSR_VAL_MASK) * 1000000ULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static int meson_measure_best_id(struct meson_msr_id *clk_msr_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int *precision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned int duration = DIV_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Start from max duration and down to min duration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = meson_measure_id(clk_msr_id, duration);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *precision = (2 * 1000000) / duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) duration -= DIV_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } while (duration >= DIV_MIN && ret == -EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static int clk_msr_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct meson_msr_id *clk_msr_id = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned int precision = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val = meson_measure_best_id(clk_msr_id, &precision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) seq_printf(s, "%d\t+/-%dHz\n", val, precision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) DEFINE_SHOW_ATTRIBUTE(clk_msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int clk_msr_summary_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct meson_msr_id *msr_table = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) unsigned int precision = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int val, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) seq_puts(s, " clock rate precision\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) seq_puts(s, "---------------------------------------------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (i = 0 ; i < CLK_MSR_MAX ; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!msr_table[i].name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) val = meson_measure_best_id(&msr_table[i], &precision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) seq_printf(s, " %-20s %10d +/-%dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) msr_table[i].name, val, precision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) DEFINE_SHOW_ATTRIBUTE(clk_msr_summary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const struct regmap_config meson_clk_msr_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .max_register = MSR_CLK_REG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int meson_msr_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) const struct meson_msr_id *match_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct meson_msr *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct dentry *root, *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) priv = devm_kzalloc(&pdev->dev, sizeof(struct meson_msr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) match_data = device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (!match_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev_err(&pdev->dev, "failed to get match data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) memcpy(priv->msr_table, match_data, sizeof(priv->msr_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (IS_ERR(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(&pdev->dev, "io resource mapping failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) &meson_clk_msr_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (IS_ERR(priv->regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) root = debugfs_create_dir("meson-clk-msr", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) clks = debugfs_create_dir("clks", root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) debugfs_create_file("measure_summary", 0444, root,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) priv->msr_table, &clk_msr_summary_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) for (i = 0 ; i < CLK_MSR_MAX ; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!priv->msr_table[i].name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) priv->msr_table[i].priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) debugfs_create_file(priv->msr_table[i].name, 0444, clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) &priv->msr_table[i], &clk_msr_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const struct of_device_id meson_msr_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .compatible = "amlogic,meson-gx-clk-measure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .data = (void *)clk_msr_gx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .compatible = "amlogic,meson8-clk-measure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .data = (void *)clk_msr_m8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .compatible = "amlogic,meson8b-clk-measure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .data = (void *)clk_msr_m8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .compatible = "amlogic,meson-axg-clk-measure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .data = (void *)clk_msr_axg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .compatible = "amlogic,meson-g12a-clk-measure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .data = (void *)clk_msr_g12a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .compatible = "amlogic,meson-sm1-clk-measure",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .data = (void *)clk_msr_sm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MODULE_DEVICE_TABLE(of, meson_msr_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static struct platform_driver meson_msr_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .probe = meson_msr_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .name = "meson_msr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .of_match_table = meson_msr_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) module_platform_driver(meson_msr_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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