^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 BayLibre, SAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Endless Mobile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/soc/amlogic/meson-canvas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define NUM_CANVAS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* DMC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DMC_CAV_LUT_DATAL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CANVAS_WIDTH_LBIT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CANVAS_WIDTH_LWID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMC_CAV_LUT_DATAH 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CANVAS_WIDTH_HBIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CANVAS_HEIGHT_BIT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CANVAS_WRAP_BIT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CANVAS_BLKMODE_BIT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CANVAS_ENDIAN_BIT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMC_CAV_LUT_ADDR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CANVAS_LUT_WR_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CANVAS_LUT_RD_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct meson_canvas {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) spinlock_t lock; /* canvas device lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 used[NUM_CANVAS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) bool supports_endianness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void canvas_write(struct meson_canvas *canvas, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) writel_relaxed(val, canvas->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static u32 canvas_read(struct meson_canvas *canvas, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return readl_relaxed(canvas->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct meson_canvas *meson_canvas_get(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct device_node *canvas_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct platform_device *canvas_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct meson_canvas *canvas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) canvas_node = of_parse_phandle(dev->of_node, "amlogic,canvas", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!canvas_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) canvas_pdev = of_find_device_by_node(canvas_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (!canvas_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) of_node_put(canvas_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) of_node_put(canvas_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * If priv is NULL, it's probably because the canvas hasn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * properly initialized. Bail out with -EINVAL because, in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * current state, this driver probe cannot return -EPROBE_DEFER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) canvas = dev_get_drvdata(&canvas_pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!canvas) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) put_device(&canvas_pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return canvas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) EXPORT_SYMBOL_GPL(meson_canvas_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int meson_canvas_config(struct meson_canvas *canvas, u8 canvas_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 addr, u32 stride, u32 height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int wrap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int blkmode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (endian && !canvas->supports_endianness) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) dev_err(canvas->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "Endianness is not supported on this SoC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) spin_lock_irqsave(&canvas->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!canvas->used[canvas_index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dev_err(canvas->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "Trying to setup non allocated canvas %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) canvas_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spin_unlock_irqrestore(&canvas->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) canvas_write(canvas, DMC_CAV_LUT_DATAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ((addr + 7) >> 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) (((stride + 7) >> 3) << CANVAS_WIDTH_LBIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) canvas_write(canvas, DMC_CAV_LUT_DATAH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ((((stride + 7) >> 3) >> CANVAS_WIDTH_LWID) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CANVAS_WIDTH_HBIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (height << CANVAS_HEIGHT_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (wrap << CANVAS_WRAP_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) (blkmode << CANVAS_BLKMODE_BIT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (endian << CANVAS_ENDIAN_BIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) canvas_write(canvas, DMC_CAV_LUT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CANVAS_LUT_WR_EN | canvas_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Force a read-back to make sure everything is flushed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) canvas_read(canvas, DMC_CAV_LUT_DATAH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) spin_unlock_irqrestore(&canvas->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) EXPORT_SYMBOL_GPL(meson_canvas_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int meson_canvas_alloc(struct meson_canvas *canvas, u8 *canvas_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) spin_lock_irqsave(&canvas->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) for (i = 0; i < NUM_CANVAS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!canvas->used[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) canvas->used[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_unlock_irqrestore(&canvas->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *canvas_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) spin_unlock_irqrestore(&canvas->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(canvas->dev, "No more canvas available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) EXPORT_SYMBOL_GPL(meson_canvas_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int meson_canvas_free(struct meson_canvas *canvas, u8 canvas_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) spin_lock_irqsave(&canvas->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!canvas->used[canvas_index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_err(canvas->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "Trying to free unused canvas %u\n", canvas_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spin_unlock_irqrestore(&canvas->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) canvas->used[canvas_index] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) spin_unlock_irqrestore(&canvas->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) EXPORT_SYMBOL_GPL(meson_canvas_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int meson_canvas_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct meson_canvas *canvas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) canvas = devm_kzalloc(dev, sizeof(*canvas), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!canvas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) canvas->reg_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (IS_ERR(canvas->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return PTR_ERR(canvas->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) canvas->supports_endianness = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) canvas->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) spin_lock_init(&canvas->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_set_drvdata(dev, canvas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct of_device_id canvas_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { .compatible = "amlogic,meson8-canvas", .data = (void *)false, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .compatible = "amlogic,meson8b-canvas", .data = (void *)false, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .compatible = "amlogic,meson8m2-canvas", .data = (void *)false, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { .compatible = "amlogic,canvas", .data = (void *)true, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MODULE_DEVICE_TABLE(of, canvas_dt_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct platform_driver meson_canvas_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .probe = meson_canvas_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .name = "amlogic-canvas",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .of_match_table = canvas_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) module_platform_driver(meson_canvas_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MODULE_DESCRIPTION("Amlogic Canvas driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MODULE_AUTHOR("Maxime Jourdan <mjourdan@baylibre.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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